Lines Matching +full:0 +full:x01f00000
23 reg = <0x0 0xffe05000 0x0 0x1000>;
26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
27 0x1 0x0 0x0 0xf8000000 0x00008000
28 0x2 0x0 0x0 0xf8010000 0x00020000
29 0x3 0x0 0x0 0xf8020000 0x00020000>;
31 nand@0,0 {
36 reg = <0x0 0x0 0x40000>;
38 partition@0 {
41 reg = <0x0 0x00100000>;
48 reg = <0x00100000 0x00100000>;
55 reg = <0x00200000 0x00400000>;
62 reg = <0x00600000 0x00500000>;
69 reg = <0x00a00000 0x00600000>;
75 reg = <0x01100000 0x00e00000>;
81 reg = <0x01f00000 0x00100000>;
87 bcsr@1,0 {
91 reg = <1 0 0x8000>;
92 ranges = <0 1 0 0x8000>;
95 pib@2,0 {
97 reg = <2 0 0x10000>;
100 pib@3,0 {
102 reg = <3 0 0x10000>;
108 ranges = <0x0 0x0 0xffe00000 0x100000>;
113 reg = <0x68>;
119 flash@0 {
123 reg = <0>;
128 reg = <0x00000000 0x00100000>;
133 reg = <0x00100000 0x00500000>;
138 reg = <0x00600000 0x00100000>;
143 reg = <0x00700000 0x00900000>;
154 phy0: ethernet-phy@0 {
155 interrupts = <1 1 0 0>;
156 reg = <0x0>;
159 interrupts = <2 1 0 0>;
160 reg = <0x1>;
163 reg = <0x4>;
167 reg = <0x5>;
173 reg = <0x11>;
197 reg = <0xe0100 0x60>;
198 ranges = <0x0 0xe0100 0x60>;
204 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
205 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
206 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
207 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
208 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
209 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
210 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
211 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
212 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
213 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
214 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
215 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
216 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
217 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
218 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
219 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
220 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
221 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
227 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
228 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
229 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
230 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
231 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
232 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
233 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
234 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
235 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
236 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
242 reg = <0 0xffe09000 0 0x1000>;
243 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
244 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
245 pcie@0 {
246 ranges = <0x2000000 0x0 0xa0000000
247 0x2000000 0x0 0xa0000000
248 0x0 0x20000000
250 0x1000000 0x0 0x0
251 0x1000000 0x0 0x0
252 0x0 0x100000>;
257 reg = <0 0xffe0a000 0 0x1000>;
258 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
259 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
260 pcie@0 {
261 ranges = <0x2000000 0x0 0xc0000000
262 0x2000000 0x0 0xc0000000
263 0x0 0x20000000
265 0x1000000 0x0 0x0
266 0x1000000 0x0 0x0
267 0x0 0x100000>;
272 ranges = <0x0 0x0 0xffe80000 0x40000>;
273 reg = <0 0xffe80000 0 0x480>;
274 brg-frequency = <0>;
275 bus-frequency = <0>;
290 qe_phy0: ethernet-phy@0 {
292 interrupts = <4 1 0 0>;
293 reg = <0x0>;
297 interrupts = <5 1 0 0>;
298 reg = <0x3>;
301 reg = <0x11>;