dts/fsl/c293pcie.dts

2  * C293 PCIE Device Tree Source
35 /include/ "c293si-pre.dtsi"
45 	ifc: memory-controller@fffe1e000 {
57 	pci0: pcie@fffe0a000 {
61 		pcie@0 {
75 		#address-cells = <1>;
76 		#size-cells = <1>;
77 		compatible = "cfi-flash";
79 		bank-width = <2>;
80 		device-width = <1>;
107 			/* 512KB for u-boot Bootloader Image and evn */
109 			label = "NOR U-Boot Image";
110 			read-only;
115 		#address-cells = <1>;
116 		#size-cells = <1>;
117 		compatible = "fsl,ifc-nand";
122 			/* 1MB for u-boot Bootloader Image */
124 			label = "NAND U-Boot Image";
125 			read-only;
148 		compatible = "fsl,c293pcie-cpld";
168 			#address-cells = <1>;
169 			#size-cells = <1>;
170 			compatible = "spansion,s25sl12801", "jedec,spi-nor";
172 			spi-max-frequency = <50000000>;
175 				/* 1MB for u-boot Bootloader Image */
178 				label = "SPI Flash U-Boot Image";
179 				read-only;
203 		phy0: ethernet-phy@0 {
208 		phy1: ethernet-phy@1 {  label
215 		phy-handle = <&phy0>;
216 		phy-connection-type = "rgmii-id";
220 		phy-handle = <&phy1>;
221 		phy-connection-type = "rgmii-id";
224 /include/ "c293si-post.dtsi"