Lines Matching +full:0 +full:x01f00000
18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
59 #size-cells = <0>;
67 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>;
69 #size-cells = <0>;
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
79 dcr-reg = <0x0e0 0x009>;
80 #address-cells = <0>;
81 #size-cells = <0>;
83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
91 dcr-reg = <0x0f0 0x009>;
92 #address-cells = <0>;
93 #size-cells = <0>;
95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
101 dcr-reg = <0x00e 0x002>;
106 dcr-reg = <0x00c 0x002>;
114 clock-frequency = <0>; /* Filled in by U-Boot */
118 dcr-reg = <0x010 0x002>;
123 dcr-reg = <0x180 0x62>;
129 interrupts = < /*TXEOB*/ 0x6 0x4
130 /*RXEOB*/ 0x7 0x4
131 /*SERR*/ 0x1 0x4
132 /*TXDE*/ 0x2 0x4
133 /*RXDE*/ 0x3 0x4
134 /*COAL TX0*/ 0x18 0x2
135 /*COAL TX1*/ 0x19 0x2
136 /*COAL TX2*/ 0x1a 0x2
137 /*COAL TX3*/ 0x1b 0x2
138 /*COAL RX0*/ 0x1c 0x2
139 /*COAL RX1*/ 0x1d 0x2
140 /*COAL RX2*/ 0x1e 0x2
141 /*COAL RX3*/ 0x1f 0x2>;
148 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
149 clock-frequency = <0>; /* Filled in by U-Boot */
153 dcr-reg = <0x012 0x002>;
156 clock-frequency = <0>; /* Filled in by U-Boot */
158 interrupts = <0x6 0x4>;
161 nor_flash@0,0 {
167 partition@0 {
169 reg = <0x00000000 0x001e0000>;
173 reg = <0x001e0000 0x00020000>;
177 reg = <0x00200000 0x01400000>;
181 reg = <0x01600000 0x00400000>;
185 reg = <0x01a00000 0x02560000>;
189 reg = <0x03f60000 0x00040000>;
193 reg = <0x03fa0000 0x00060000>;
197 ndfc@1,0 {
200 ccr = <0x00003000>;
201 bank-settings = <0x80002222>;
208 partition@0 {
210 reg = <0x00000000 0x00200000>;
214 reg = <0x00200000 0x00100000>;
218 reg = <0x00300000 0x00300000>;
222 reg = <0x00600000 0x01900000>;
226 reg = <0x01f00000 0x00020000>;
230 reg = <0x01f20000 0x060E0000>;
239 reg = <0xef600200 0x00000008>;
240 virtual-reg = <0xef600200>;
241 clock-frequency = <0>; /* Filled in by U-Boot */
242 current-speed = <0>; /* Filled in by U-Boot */
244 interrupts = <0x0 0x4>;
250 reg = <0xef600300 0x00000008>;
251 virtual-reg = <0xef600300>;
252 clock-frequency = <0>; /* Filled in by U-Boot */
253 current-speed = <0>; /* Filled in by U-Boot */
255 interrupts = <0x1 0x4>;
260 reg = <0xef600400 0x00000014>;
262 interrupts = <0x2 0x4>;
264 #size-cells = <0>;
265 index = <0>;
270 reg = <0xef600500 0x00000014>;
272 interrupts = <0x3 0x4>;
274 #size-cells = <0>;
280 reg = <0xef600900 0x00000008>;
286 reg = <0xef600920 0x00000008>;
292 reg = <0xef600e50 0x00000030>;
297 reg = <0xef600f50 0x00000030>;
304 interrupts = <0x0 0x1>;
306 #address-cells = <0>;
307 #size-cells = <0>;
308 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
309 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
310 reg = <0xef600a00 0x00000070>;
313 mal-tx-channel = <0>;
314 mal-rx-channel = <0>;
315 cell-index = <0>;
321 phy-map = <0x00000000>;
323 rgmii-channel = <0>;
325 tah-channel = <0>;
334 interrupts = <0x0 0x1>;
336 #address-cells = <0>;
337 #size-cells = <0>;
338 interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4
339 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
340 reg = <0xef600b00 0x00000070>;
351 phy-map = <0x00000000>;
365 interrupts = <0x0 0x1>;
367 #address-cells = <0>;
368 #size-cells = <0>;
369 interrupt-map = </*Status*/ 0x0 &UIC0 0x15 0x4
370 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
371 reg = <0xef600c00 0x00000070>;
383 phy-map = <0x00000000>;
385 rgmii-channel = <0>;
395 interrupts = <0x0 0x1>;
397 #address-cells = <0>;
398 #size-cells = <0>;
399 interrupt-map = </*Status*/ 0x0 &UIC0 0x16 0x4
400 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
401 reg = <0xef600d00 0x00000070>;
413 phy-map = <0x00000000>;