boot/dts/ebony.dts

21 	dcr-parent = <&{/cpus/cpu@0}>;
32 		#size-cells = <0>;
34 		cpu@0 {
37 			reg = <0x00000000>;
38 			clock-frequency = <0>; // Filled in by zImage
39 			timebase-frequency = <0>; // Filled in by zImage
51 		reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
57 		cell-index = <0>;
58 		dcr-reg = <0x0c0 0x009>;
59 		#address-cells = <0>;
60 		#size-cells = <0>;
69 		dcr-reg = <0x0d0 0x009>;
70 		#address-cells = <0>;
71 		#size-cells = <0>;
73 		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
79 		dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
88 		clock-frequency = <0>; // Filled in by zImage
92 			dcr-reg = <0x010 0x002>;
98 			dcr-reg = <0x020 0x008 0x00a 0x001>;
104 			dcr-reg = <0x100 0x027>;
109 			dcr-reg = <0x180 0x062>;
113 			interrupts = <0x0 0x1 0x2 0x3 0x4>;
115 			#address-cells = <0>;
116 			#size-cells = <0>;
117 			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
118 					 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
119 					 /*SERR*/  0x2 &UIC1 0x0 0x4
120 					 /*TXDE*/  0x3 &UIC1 0x1 0x4
121 					 /*RXDE*/  0x4 &UIC1 0x2 0x4>;
122 			interrupt-map-mask = <0xffffffff>;
131 			ranges = <0x00000000 0x00000001 0x00000000 0x80000000
132 				  0x80000000 0x00000001 0x80000000 0x80000000>;
133 			dcr-reg = <0x090 0x00b>;
135 			interrupts = <0x7 0x4>;
136 			clock-frequency = <0>; // Filled in by zImage
140 				dcr-reg = <0x012 0x002>;
143 				clock-frequency = <0>; // Filled in by zImage
147 				interrupts = <0x5 0x4>;
150 				small-flash@0,80000 {
153 					reg = <0x00000000 0x00080000 0x00080000>;
156 					partition@0 {
158 						reg = <0x00000000 0x00080000>;
163 				nvram@1,0 {
166 					#bytes = <0x2000>;
167 					reg = <0x00000001 0x00000000 0x00002000>;
170 				large-flash@2,0 {
173 					reg = <0x00000002 0x00000000 0x00400000>;
176 					partition@0 {
178 						reg = <0x00000000 0x00380000>;
182 						reg = <0x00380000 0x00080000>;
186 				ir@3,0 {
187 					reg = <0x00000003 0x00000000 0x00000010>;
190 				fpga@7,0 {
192 					reg = <0x00000007 0x00000000 0x00000010>;
193 					virtual-reg = <0xe8300000>;
200 				reg = <0x40000200 0x00000008>;
201 				virtual-reg = <0xe0000200>;
205 				interrupts = <0x0 0x4>;
211 				reg = <0x40000300 0x00000008>;
212 				virtual-reg = <0xe0000300>;
216 				interrupts = <0x1 0x4>;
222 				reg = <0x40000400 0x00000014>;
224 				interrupts = <0x2 0x4>;
229 				reg = <0x40000500 0x00000014>;
231 				interrupts = <0x3 0x4>;
237 				reg = <0x40000700 0x00000020>;
242 				reg = <0x40000780 0x0000000c>;
249 				interrupts = <0x1c 0x4 0x1d 0x4>;
250 				reg = <0x40000800 0x00000070>;
253 				mal-tx-channel = <0 1>;
254 				mal-rx-channel = <0>;
255 				cell-index = <0>;
260 				phy-map = <0x00000001>;
262 				zmii-channel = <0>;
268 				interrupts = <0x1e 0x4 0x1f 0x4>;
269 				reg = <0x40000900 0x00000070>;
279 				phy-map = <0x00000001>;
287 				reg = <0x40000a00 0x000000d4>;
289 				interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
301 			reg = <0x00000002 0x0ec00000 0x00000008	/* Config space access */
302 			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
303 			       0x00000002 0x0ed00000 0x00000004     /* Special cycles */
304 			       0x00000002 0x0ec80000 0x000000f0	/* Internal registers */
305 			       0x00000002 0x0ec80100 0x000000fc>;	/* Internal messaging registers */
310 			ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
311 				  0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
313 			/* Inbound 2GB range starting at 0 */
314 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
317 			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
320 				0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
323 				0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
326 				0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
329 				0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8