Lines Matching +full:u +full:- +full:boot
1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
46 d-cache-size = <32768>;
47 dcr-controller;
48 dcr-access-method = "native";
49 next-level-cache = <&L2C0>;
55 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
58 UIC0: interrupt-controller0 {
59 compatible = "ibm,uic-460gt","ibm,uic";
60 interrupt-controller;
61 cell-index = <0>;
62 dcr-reg = <0x0c0 0x009>;
63 #address-cells = <0>;
64 #size-cells = <0>;
65 #interrupt-cells = <2>;
68 UIC1: interrupt-controller1 {
69 compatible = "ibm,uic-460gt","ibm,uic";
70 interrupt-controller;
71 cell-index = <1>;
72 dcr-reg = <0x0d0 0x009>;
73 #address-cells = <0>;
74 #size-cells = <0>;
75 #interrupt-cells = <2>;
77 interrupt-parent = <&UIC0>;
80 UIC2: interrupt-controller2 {
81 compatible = "ibm,uic-460gt","ibm,uic";
82 interrupt-controller;
83 cell-index = <2>;
84 dcr-reg = <0x0e0 0x009>;
85 #address-cells = <0>;
86 #size-cells = <0>;
87 #interrupt-cells = <2>;
89 interrupt-parent = <&UIC0>;
92 UIC3: interrupt-controller3 {
93 compatible = "ibm,uic-460gt","ibm,uic";
94 interrupt-controller;
95 cell-index = <3>;
96 dcr-reg = <0x0f0 0x009>;
97 #address-cells = <0>;
98 #size-cells = <0>;
99 #interrupt-cells = <2>;
101 interrupt-parent = <&UIC0>;
105 compatible = "ibm,sdr-460gt";
106 dcr-reg = <0x00e 0x002>;
110 compatible = "ibm,cpr-460gt";
111 dcr-reg = <0x00c 0x002>;
115 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
116 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
118 cache-line-size = <32>; /* 32 bytes */
119 cache-size = <262144>; /* L2, 256K */
120 interrupt-parent = <&UIC1>;
125 compatible = "ibm,plb-460gt", "ibm,plb4";
126 #address-cells = <2>;
127 #size-cells = <1>;
129 clock-frequency = <0>; /* Filled in by U-Boot */
132 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
133 dcr-reg = <0x010 0x002>;
137 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
139 interrupt-parent = <&UIC0>;
144 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
145 dcr-reg = <0x180 0x062>;
146 num-tx-chans = <3>;
147 num-rx-chans = <24>;
148 #address-cells = <0>;
149 #size-cells = <0>;
150 interrupt-parent = <&UIC2>;
156 desc-base-addr-high = <0x8>;
160 compatible = "ibm,opb-460gt", "ibm,opb";
161 #address-cells = <1>;
162 #size-cells = <1>;
164 clock-frequency = <0>; /* Filled in by U-Boot */
167 compatible = "ibm,ebc-460gt", "ibm,ebc";
168 dcr-reg = <0x012 0x002>;
169 #address-cells = <2>;
170 #size-cells = <1>;
171 clock-frequency = <0>; /* Filled in by U-Boot */
172 /* ranges property is supplied by U-Boot */
174 interrupt-parent = <&UIC1>;
177 compatible = "amd,s29gl256n", "cfi-flash";
178 bank-width = <2>;
180 #address-cells = <1>;
181 #size-cells = <1>;
203 label = "u-boot";
213 virtual-reg = <0xef600300>;
214 clock-frequency = <0>; /* Filled in by U-Boot */
215 current-speed = <0>; /* Filled in by U-Boot */
216 interrupt-parent = <&UIC1>;
221 compatible = "ibm,iic-460gt", "ibm,iic";
223 interrupt-parent = <&UIC0>;
225 #address-cells = <1>;
226 #size-cells = <0>;
230 interrupt-parent = <&UIC1>;
236 compatible = "ibm,iic-460gt", "ibm,iic";
238 interrupt-parent = <&UIC0>;
242 TAH0: emac-tah@ef601350 {
243 compatible = "ibm,tah-460gt", "ibm,tah";
247 TAH1: emac-tah@ef601450 {
248 compatible = "ibm,tah-460gt", "ibm,tah";
254 compatible = "ibm,emac-460gt", "ibm,emac4sync";
255 interrupt-parent = <&EMAC0>;
257 #interrupt-cells = <1>;
258 #address-cells = <0>;
259 #size-cells = <0>;
260 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
263 local-mac-address = [000000000000]; /* Filled in by U-Boot */
264 mal-device = <&MAL0>;
265 mal-tx-channel = <0>;
266 mal-rx-channel = <0>;
267 cell-index = <0>;
268 max-frame-size = <9000>;
269 rx-fifo-size = <4096>;
270 tx-fifo-size = <2048>;
271 rx-fifo-size-gige = <16384>;
272 phy-mode = "sgmii";
273 phy-map = <0xffffffff>;
274 gpcs-address = <0x0000000a>;
275 tah-device = <&TAH0>;
276 tah-channel = <0>;
277 has-inverted-stacr-oc;
278 has-new-stacr-staopc;
283 compatible = "ibm,emac-460gt", "ibm,emac4sync";
284 interrupt-parent = <&EMAC1>;
286 #interrupt-cells = <1>;
287 #address-cells = <0>;
288 #size-cells = <0>;
289 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
292 local-mac-address = [000000000000]; /* Filled in by U-Boot */
293 mal-device = <&MAL0>;
294 mal-tx-channel = <1>;
295 mal-rx-channel = <8>;
296 cell-index = <1>;
297 max-frame-size = <9000>;
298 rx-fifo-size = <4096>;
299 tx-fifo-size = <2048>;
300 rx-fifo-size-gige = <16384>;
301 phy-mode = "sgmii";
302 phy-map = <0x00000000>;
303 gpcs-address = <0x0000000b>;
304 tah-device = <&TAH1>;
305 tah-channel = <1>;
306 has-inverted-stacr-oc;
307 has-new-stacr-staopc;
308 mdio-device = <&EMAC0>;
313 compatible = "ibm,emac-460gt", "ibm,emac4sync";
314 interrupt-parent = <&EMAC2>;
316 #interrupt-cells = <1>;
317 #address-cells = <0>;
318 #size-cells = <0>;
319 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
322 local-mac-address = [000000000000]; /* Filled in by U-Boot */
323 mal-device = <&MAL0>;
324 mal-tx-channel = <2>;
325 mal-rx-channel = <16>;
326 cell-index = <2>;
327 max-frame-size = <9000>;
328 rx-fifo-size = <4096>;
329 tx-fifo-size = <2048>;
330 rx-fifo-size-gige = <16384>;
331 tx-fifo-size-gige = <16384>; /* emac2&3 only */
332 phy-mode = "sgmii";
333 phy-map = <0x00000001>;
334 gpcs-address = <0x0000000C>;
335 has-inverted-stacr-oc;
336 has-new-stacr-staopc;
337 mdio-device = <&EMAC0>;