Lines Matching +full:0 +full:x07ffffff
41 #define Fpustatus_register Fpu_register[0]
45 #define NOTRAP 0
58 #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0
81 if ((Dallp2(dbl_valuep2)--) == 0) Dallp1(dbl_valuep1)--
86 aflags=(Fpu_register[0])>>27; /* assumes zero fill. 32 bit */ \
87 Fpu_register[0] |= bflags; \
104 * need to restore Fpu_register[0] in decode_fpu()
107 bflags=(Fpu_register[0] & 0xf8000000); in decode_fpu()
108 Fpu_register[0] &= 0x07ffffff; in decode_fpu()
139 * codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds in decode_fpu()
140 * another, 0x2b. Only these have the low order bit set. in decode_fpu()
155 excp = fpudispatch(current_ir,excptype,0,Fpu_register); in decode_fpu()
257 Set_parmfield(Fpu_register[exception_index],0); in decode_fpu()
339 printk("%s(%d) Unknown FPU exception 0x%x\n", __FILE__, in decode_fpu()