parisc/kernel/perf_asm.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /*    low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
5  *    Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6  *    Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
46 	sync                            ; follow ERS
100 ;*	%r24  - original DR2 value
101 ;*	%r1   - scratch
102 ;*  %r29  - scratch
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
132 ; Cacheline start (32-byte cacheline)
140 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
141 	blr  		%r1,%r0		; branch to 8-instruction sequence
145 ; Cacheline start (32-byte cacheline)
163 	sync
173 	; RDR 2 read sequence
175 	SFDIAG		(2)
180 	STDIAG		(2)
199 	sync
211 	sync
223 	sync
307 	sync
331 	sync
343 	sync
391 	sync
403 	sync
415 	sync
427 	sync
439 	sync
451 	sync
487 	sync
499 	sync
523 	sync
549 ;*	This routine moves data to the RDR's.  The double-word that
556 ;*	arg1 = 64-bit value to write
557 ;*	%r24 - DR2 | DR2_SLOW_RET
558 ;*	%r23 - original DR2 value
572 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
581 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
582 	blr		    %r1,%r0	; branch to 8-instruction sequence
588 	sync				; RDR 0 write sequence
600 	sync
610 	; RDR 2 write sequence
612 	sync
614 	STDIAG		(2)
624 	sync
636 	sync
648 	sync
660 	sync
672 	sync
684 	sync
696 	sync
708 	sync
720 	sync
732 	sync
744 	sync
756 	sync
768 	sync
780 	sync
792 	sync
804 	sync
816 	sync
828 	sync
840 	sync
852 	sync
864 	sync
876 	sync
888 	sync
900 	sync
912 	sync
924 	sync
936 	sync
948 	sync
960 	sync
998 ;*	%r24 - original DR2 value
999 ;*	%r23 - DR2 | DR2_SLOW_RET
1000 ;*	%r1  - scratch
1011 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1025 ; Start of next 32-byte cacheline
1033 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
1034 	blr 		%r1,%r0		; branch to 8-instruction sequence
1038 ; Start of next 32-byte cacheline
1058 	sync				; RDR 2 read sequence
1067 	sync				; RDR 3 read sequence
1076 	sync				; RDR 4 read sequence
1085 	sync				; RDR 5 read sequence
1094 	sync				; RDR 6 read sequence
1103 	sync				; RDR 7 read sequence
1184 	sync				; RDR 16 read sequence
1220 	sync				; RDR 20 read sequence
1229 	sync				; RDR 21 read sequence
1238 	sync				; RDR 22 read sequence
1247 	sync				; RDR 23 read sequence
1256 	sync				; RDR 24 read sequence
1265 	sync				; RDR 25 read sequence
1292 	sync				; RDR 28 read sequence
1341 ;*	This routine moves data to the RDR's.  The double-word that
1356 ;*	%r24 - DR2 | DR2_SLOW_RET
1357 ;*	%r23 - original DR2 value
1367 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1377 	shladd		arg0,2,%r0,%r1	; %r1 = 4 * RDR number
1378 	blr		%r1,%r0		; branch to 8-instruction sequence
1382 ; 32-byte cachline aligned
1385 	sync				; RDR 0 write sequence
1394 	sync				; RDR 1 write sequence
1403 	sync				; RDR 2 write sequence
1405 	STDIAG		(2)
1412 	sync				; RDR 3 write sequence
1421 	sync				; RDR 4 write sequence
1430 	sync				; RDR 5 write sequence
1439 	sync				; RDR 6 write sequence
1448 	sync				; RDR 7 write sequence
1457 	sync				; RDR 8 write sequence
1466 	sync				; RDR 9 write sequence
1475 	sync				; RDR 10 write sequence
1484 	sync				; RDR 11 write sequence
1493 	sync				; RDR 12 write sequence
1502 	sync				; RDR 13 write sequence
1511 	sync				; RDR 14 write sequence
1520 	sync				; RDR 15 write sequence
1529 	sync				; RDR 16 write sequence
1538 	sync				; RDR 17 write sequence
1547 	sync				; RDR 18 write sequence
1556 	sync				; RDR 19 write sequence
1565 	sync				; RDR 20 write sequence
1574 	sync				; RDR 21 write sequence
1583 	sync				; RDR 22 write sequence
1592 	sync				; RDR 23 write sequence
1601 	sync				; RDR 24 write sequence
1610 	sync				; RDR 25 write sequence
1619 	sync				; RDR 26 write sequence
1628 	sync				; RDR 27 write sequence
1637 	sync				; RDR 28 write sequence
1646 	sync				; RDR 29 write sequence
1655 	sync				; RDR 30 write sequence
1664 	sync				; RDR 31 write sequence