Lines Matching +full:4 +full:l
14 #define PDC_PAT_CELL 64L /* Interface for gaining and
16 #define PDC_PAT_CELL_GET_NUMBER 0L /* Return Cell number */
17 #define PDC_PAT_CELL_GET_INFO 1L /* Returns info about Cell */
18 #define PDC_PAT_CELL_MODULE 2L /* Returns info about Module */
19 #define PDC_PAT_CELL_SET_ATTENTION 9L /* Set Cell Attention indicator */
20 #define PDC_PAT_CELL_NUMBER_TO_LOC 10L /* Cell Number -> Location */
21 #define PDC_PAT_CELL_WALK_FABRIC 11L /* Walk the Fabric */
22 #define PDC_PAT_CELL_GET_RDT_SIZE 12L /* Return Route Distance Table Sizes */
23 #define PDC_PAT_CELL_GET_RDT 13L /* Return Route Distance Tables */
24 #define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
25 #define PDC_PAT_CELL_SET_LOCAL_PDH 15L /* Write Local PDH Buffer */
26 #define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
27 #define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
28 #define PDC_PAT_CELL_GET_DBG_INFO 128L /* Return DBG Buffer Info */
29 #define PDC_PAT_CELL_CHANGE_ALIAS 129L /* Change Non-Equivalent Alias Chacking */
33 ** Arg to PDC_PAT_CELL_MODULE memaddr[4]
46 #define PAT_ENTITY_LBA 4 /* local bus adapter */
53 #define PAT_LMMIO 1 /* < 4G MMIO Space */
54 #define PAT_GMMIO 2 /* > 4G MMIO Space */
56 #define PAT_PIOP 4 /* Postable I/O Port Space */
65 #define PDC_PAT_CHASSIS_LOG 65L
66 #define PDC_PAT_CHASSIS_WRITE_LOG 0L /* Write Log Entry */
67 #define PDC_PAT_CHASSIS_READ_LOG 1L /* Read Log Entry */
72 #define PDC_PAT_COMPLEX 66L
76 #define PDC_PAT_CPU 67L
77 #define PDC_PAT_CPU_INFO 0L /* Return CPU config info */
78 #define PDC_PAT_CPU_DELETE 1L /* Delete CPU */
79 #define PDC_PAT_CPU_ADD 2L /* Add CPU */
80 #define PDC_PAT_CPU_GET_NUMBER 3L /* Return CPU Number */
81 #define PDC_PAT_CPU_GET_HPA 4L /* Return CPU HPA */
82 #define PDC_PAT_CPU_STOP 5L /* Stop CPU */
83 #define PDC_PAT_CPU_RENDEZVOUS 6L /* Rendezvous CPU */
84 #define PDC_PAT_CPU_GET_CLOCK_INFO 7L /* Return CPU Clock info */
85 #define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
86 #define PDC_PAT_CPU_GET_PDC_ENTRYPOINT 11L /* Return PDC Entry point */
87 #define PDC_PAT_CPU_PLUNGE_FABRIC 128L /* Plunge Fabric */
88 #define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache
92 #define PDC_PAT_EVENT 68L
93 #define PDC_PAT_EVENT_GET_CAPS 0L /* Get Capabilities */
94 #define PDC_PAT_EVENT_SET_MODE 1L /* Set Notification Mode */
95 #define PDC_PAT_EVENT_SCAN 2L /* Scan Event */
96 #define PDC_PAT_EVENT_HANDLE 3L /* Handle Event */
97 #define PDC_PAT_EVENT_GET_NB_CALL 4L /* Get Non-Blocking call Args */
103 #define PDC_PAT_HPMC 70L
104 #define PDC_PAT_HPMC_RENDEZ_CPU 0L /* go into spin loop */
105 #define PDC_PAT_HPMC_SET_PARAMS 1L /* Allows OS to specify intr which PDC
110 #define HPMC_SET_PARAMS_INTR 1L /* Rendezvous Interrupt */
111 #define HPMC_SET_PARAMS_WAKE 2L /* Wake up processor */
116 #define PDC_PAT_IO 71L
117 #define PDC_PAT_IO_GET_SLOT_STATUS 5L /* Get Slot Status Info*/
118 #define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
120 #define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from
122 #define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
124 #define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path
126 #define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L /* Read Host Bridge State Info */
127 #define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
128 #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table
130 #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE 16L /* Get PCI INT Routing Table */
131 #define PDC_PAT_IO_GET_HINT_TABLE_SIZE 17L /* Get Hint Table Size */
132 #define PDC_PAT_IO_GET_HINT_TABLE 18L /* Get Hint Table */
133 #define PDC_PAT_IO_PCI_CONFIG_READ 19L /* PCI Config Read */
134 #define PDC_PAT_IO_PCI_CONFIG_WRITE 20L /* PCI Config Write */
135 #define PDC_PAT_IO_GET_NUM_IO_SLOTS 21L /* Get Number of I/O Bay Slots in
137 #define PDC_PAT_IO_GET_LOC_IO_SLOTS 22L /* Get Physical Location of I/O */
139 #define PDC_PAT_IO_BAY_STATUS_INFO 28L /* Get I/O Bay Slot Status Info */
140 #define PDC_PAT_IO_GET_PROC_VIEW 29L /* Get Processor view of IO address */
141 #define PDC_PAT_IO_PROG_SBA_DIR_RANGE 30L /* Program directed range */
146 #define PDC_PAT_MEM 72L
147 #define PDC_PAT_MEM_PD_INFO 0L /* Return PDT info for PD */
148 #define PDC_PAT_MEM_PD_CLEAR 1L /* Clear PDT for PD */
149 #define PDC_PAT_MEM_PD_READ 2L /* Read PDT entries for PD */
150 #define PDC_PAT_MEM_PD_RESET 3L /* Reset clear bit for PD */
151 #define PDC_PAT_MEM_CELL_INFO 5L /* Return PDT info For Cell */
152 #define PDC_PAT_MEM_CELL_CLEAR 6L /* Clear PDT For Cell */
153 #define PDC_PAT_MEM_CELL_READ 7L /* Read PDT entries For Cell */
154 #define PDC_PAT_MEM_CELL_RESET 8L /* Reset clear bit For Cell */
155 #define PDC_PAT_MEM_SETGM 9L /* Set Good Memory value */
156 #define PDC_PAT_MEM_ADD_PAGE 10L /* ADDs a page to the cell */
157 #define PDC_PAT_MEM_ADDRESS 11L /* Get Physical Location From */
159 #define PDC_PAT_MEM_GET_TXT_SIZE 12L /* Get Formatted Text Size */
160 #define PDC_PAT_MEM_GET_PD_TXT 13L /* Get PD Formatted Text */
161 #define PDC_PAT_MEM_GET_CELL_TXT 14L /* Get Cell Formatted Text */
162 #define PDC_PAT_MEM_RD_STATE_INFO 15L /* Read Mem Module State Info*/
163 #define PDC_PAT_MEM_CLR_STATE_INFO 16L /*Clear Mem Module State Info*/
164 #define PDC_PAT_MEM_CLEAN_RANGE 128L /*Clean Mem in specific range*/
165 #define PDC_PAT_MEM_GET_TBL_SIZE 131L /* Get Memory Table Size */
166 #define PDC_PAT_MEM_GET_TBL 132L /* Get Memory Table */
171 #define PDC_PAT_NVOLATILE 73L
172 #define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */
173 #define PDC_PAT_NVOLATILE_WRITE 1L /* Write Non-Volatile Memory */
174 #define PDC_PAT_NVOLATILE_GET_SIZE 2L /* Return size of NVM */
175 #define PDC_PAT_NVOLATILE_VERIFY 3L /* Verify contents of NVM */
176 #define PDC_PAT_NVOLATILE_INIT 4L /* Initialize NVM */
179 #define PDC_PAT_PD 74L /* Protection Domain Info */
180 #define PDC_PAT_PD_GET_ADDR_MAP 0L /* Get Address Map */
181 #define PDC_PAT_PD_GET_PDC_INTERF_REV 1L /* Get PDC Interface Revisions */
187 #define PDC_PAT_CAPABILITY_BIT_PDC_IODC_32 (1UL << 4)
197 #define PAT_MEMTYPE_FIRMWARE 4
205 #define PDC_PAT_REGISTER_TOC 75L
206 #define PDC_PAT_TOC_REGISTER_VECTOR 0L /* Register TOC Vector */
207 #define PDC_PAT_TOC_READ_VECTOR 1L /* Read TOC Vector */
210 #define PDC_PAT_SYSTEM_INFO 76L
274 u64 source:4; /* for mem: always 0x07 */
275 u64 source_detail:4; /* for mem: always 0x04 (SIMM or DIMM) */
284 unsigned int pages; /* Length in 4K pages */
304 * 4 = local bus adapter, 5 = processor bus converter,
311 * number of 4K pages a module occupies starting at conf_base_addr
345 } xbc[8*4];