Lines Matching +full:0 +full:xda
31 #define MAX_DMA_ADDRESS (~0UL)
41 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
42 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
43 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
45 #define DMA_AUTOINIT 0x10
48 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
49 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
52 #define DMA1_CMD_REG 0x08 /* command register (w) */
53 #define DMA1_STAT_REG 0x08 /* status register (r) */
54 #define DMA1_REQ_REG 0x09 /* request register (w) */
55 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
56 #define DMA1_MODE_REG 0x0B /* mode register (w) */
57 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
58 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
59 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
60 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
61 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
62 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
64 #define DMA2_CMD_REG 0xD0 /* command register (w) */
65 #define DMA2_STAT_REG 0xD0 /* status register (r) */
66 #define DMA2_REQ_REG 0xD2 /* request register (w) */
67 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
68 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
69 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
70 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
71 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
72 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
73 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
74 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
78 return 0; in claim_dma_lock()
130 #define request_dma(dmanr, device_id) (0)
133 * Write 0 for LSB/MSB, 1 for MSB/LSB access.