Lines Matching +full:0 +full:x1b00
34 l.movhi gpr,0x0
41 #define UART_BASE_ADD 0x90000000
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
164 l.lwz reg,0(t1)
169 l.lwz reg,0(t1)
181 l.lwz r10,0(r30)
187 l.lwz r10,0(r30)
208 * r12 - syscall 0, since we didn't come from syscall
225 l.sfeqi r30,0 ;\
278 * l.ori r3,r0,0x1 ;\
280 * l.movhi r3,hi(0xf0000100) ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
298 l.addi r1,r3,0x0 ;\
299 l.addi r10,r9,0x0 ;\
306 l.andi r3,r3,0x1f00 ;\
318 l.addi r3,r1,0x0 ;\
319 l.addi r9,r10,0x0 ;\
360 /* ---[ 0x100: RESET exception ]----------------------------------------- */
361 .org 0x100
370 /* ---[ 0x200: BUS exception ]------------------------------------------- */
371 .org 0x200
375 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
376 .org 0x300
380 // DEBUG_TLB_PROBE(0x300)
381 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
384 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
385 .org 0x400
389 // DEBUG_TLB_PROBE(0x400)
390 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
393 /* ---[ 0x500: Timer exception ]----------------------------------------- */
394 .org 0x500
397 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
398 .org 0x600
401 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
402 .org 0x700
405 /* ---[ 0x800: External interrupt exception ]---------------------------- */
406 .org 0x800
409 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
410 .org 0x900
414 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
415 .org 0xa00
419 /* ---[ 0xb00: Range exception ]----------------------------------------- */
420 .org 0xb00
423 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
424 .org 0xc00
427 /* ---[ 0xd00: Floating point exception ]--------------------------------- */
428 .org 0xd00
431 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
432 .org 0xe00
436 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
437 .org 0xf00
440 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
441 .org 0x1000
444 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
445 .org 0x1100
448 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
449 .org 0x1200
452 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
453 .org 0x1300
456 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
457 .org 0x1400
460 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
461 .org 0x1500
464 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
465 .org 0x1600
468 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
469 .org 0x1700
472 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
473 .org 0x1800
476 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
477 .org 0x1900
480 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
481 .org 0x1a00
484 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
485 .org 0x1b00
488 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
489 .org 0x1c00
492 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
493 .org 0x1d00
496 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
497 .org 0x1e00
500 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
501 .org 0x1f00
504 .org 0x2000
525 l.ori r3,r0,0x1
583 l.ori r4,r0,0x0
598 l.sw (0)(r28),r0
620 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
648 l.lwz r3,0(r25) /* load magic from fdt into r3 */
709 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
710 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
713 l.mtspr r5,r0,0x0
714 l.mtspr r6,r0,0x0
747 l.ori r25,r25,0xffff
767 l.lwz r3,0(r4)
779 l.lwz r10,0(r30)
824 .align 0x2000
842 If BS=0, 16;
862 l.addi r6,r0,0
908 If BS=0, 16;
928 l.addi r6,r0,0
946 #define DTLB_UP_CONVERT_MASK 0x3fa
947 #define ITLB_UP_CONVERT_MASK 0x3a
953 #define DTLB_SMP_CONVERT_MASK 0x3fb
954 #define ITLB_SMP_CONVERT_MASK 0x3b
960 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
963 #define DTLB_MR_MASK 0xfffff001
972 #define DTLB_TR_MASK 0xfffff332
976 #define VPN_MASK 0xfffff000
977 #define PPN_MASK 0xfffff000
982 #if 0
985 l.sfeqi r6,0 // r6 == 0x1 --> SM
1005 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
1010 l.ori r5, r0, 0x1
1016 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1020 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1022 /* set up DTLB with no translation for EA <= 0xbfffffff */
1023 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
1024 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1030 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1034 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1057 #define ITLB_MR_MASK 0xfffff001
1063 #define ITLB_TR_MASK 0xfffff050
1066 #define VPN_MASK 0xffffe000
1067 #define PPN_MASK 0xffffe000
1078 #if 0
1081 l.sfeqi r6,0 // r6 == 0x1 --> SM
1092 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1097 l.ori r5, r0, 0x1
1103 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1107 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1110 * set up ITLB with no translation for EA <= 0x0fffffff
1116 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
1117 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1123 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1127 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1171 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1172 l.slli r4,r4,0x2 // to get address << 2
1179 l.lwz r3,0x0(r4) // get *pmd value
1182 l.addi r3,r0,0xffffe000 // PAGE_MASK
1188 l.lwz r4,0x0(r4) // get **pmd value
1190 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1191 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1192 l.slli r3,r3,0x2 // to get address << 2
1194 l.lwz r3,0x0(r3) // this is pte at last
1198 l.andi r4,r3,0x1
1201 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1210 l.ori r3, r0, 0x1
1214 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1217 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1221 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1222 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1223 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1251 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1252 l.slli r4,r4,0x2 // to get address << 2
1259 l.lwz r3,0x0(r4) // get *pmd value
1262 l.addi r3,r0,0xffffe000 // PAGE_MASK
1269 l.lwz r4,0x0(r4) // get **pmd value
1271 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1272 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1273 l.slli r3,r3,0x2 // to get address << 2
1275 l.lwz r3,0x0(r3) // this is pte at last
1280 l.andi r4,r3,0x1
1283 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1288 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1295 l.ori r3, r0, 0x1
1299 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1310 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1312 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1316 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1317 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1318 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1361 l.andi r5,r5,0xff
1362 l.sfnei r5,0
1367 l.andi r7,r7,0xff
1368 l.sw 0(r4),r7
1371 l.addi r6,r0,0x20
1373 l.andi r5,r5,0x20
1379 l.sb 0(r4),r7
1382 l.addi r6,r0,0x60
1384 l.andi r5,r5,0x60
1410 2: l.lbz r7,0(r3)
1411 l.sfeqi r7,0x0
1420 l.addi r3,r3,0x1
1445 l.addi r8,r8,-0x4
1447 l.andi r7,r7,0xf
1449 /* don't skip the last zero if number == 0x0 */
1450 l.sfeqi r8,0x4
1461 l.andi r7,r7,0xf
1466 l.sfgtui r7,0x9
1469 l.addi r7,r7,0x27
1473 l.addi r7,r7,0x30
1477 l.addi r8,r8,-0x4
1512 l.addi r4,r0,0x7
1513 l.sb 0x2(r3),r4
1515 l.addi r4,r0,0x0
1516 l.sb 0x1(r3),r4
1518 l.addi r4,r0,0x3
1519 l.sb 0x3(r3),r4
1522 l.ori r4,r5,0x80
1523 l.sb 0x3(r3),r4
1524 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1526 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1528 l.sb 0x3(r3),r5
1534 .align 0x1000
1538 .space 0x800
1547 .string "\r\nRunarunaround: Unhandled exception 0x\0"
1550 .string ": EPC=0x\0"
1553 .string "\r\n\0"