Lines Matching +full:0 +full:x1b00
48 l.addi r2,r1,0 /* move sp to fp */ ;\
51 l.ori r1,r2,0 /* restore sp */ ;\
62 l.addi r2,r1,0 /* move sp to fp */ ;\
65 l.ori r1,r2,0 /* restore sp */ ;\
218 l.addi r3,r1,0 ;\
230 l.sw 0(reg),r0
242 /* ---[ 0x100: RESET exception ]----------------------------------------- */
246 l.andi r0,r0,0
248 /* ---[ 0x200: BUS exception ]------------------------------------------- */
254 l.addi r3,r1,0 /* pt_regs */
259 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
269 l.ori r5,r0,0x300 // exception vector
271 l.addi r3,r1,0 // pt_regs
276 l.lwz r6,0(r6) // instruction that caused pf
279 l.sfeqi r6,0 // l.j
287 l.sfeqi r6,0x11 // l.jr
289 l.sfeqi r6,0x12 // l.jalr
299 l.lwz r6,0(r6) // instruction that caused pf
313 l.lwz r6,0(r6) // instruction that caused pf
317 l.sfgeui r6,0x33 // check opcode for write access
319 l.sfleui r6,0x37
321 l.ori r6,r0,0x1 // write access
324 1: l.ori r6,r0,0x0 // !write access
333 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
343 l.ori r5,r0,0x400 // exception vector
345 l.addi r3,r1,0 // pt_regs
347 l.ori r6,r0,0x0 // !write access
356 /* ---[ 0x500: Timer exception ]----------------------------------------- */
361 l.addi r3,r1,0 /* pt_regs */
366 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
372 l.addi r3,r1,0 /* pt_regs */
377 #if 0
380 l.addi r2,r4,0
384 l.lwz r3,0(r5) /* Load insn */
387 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
389 l.sfeqi r4,0x01
391 l.sfeqi r4,0x03
393 l.sfeqi r4,0x04
395 l.sfeqi r4,0x11
397 l.sfeqi r4,0x12
416 l.andi r4,r4,0x7c
421 l.lwz r5,0(r4)
430 l.sfeqi r4,0x26
432 l.sfeqi r4,0x25
434 l.sfeqi r4,0x22
436 l.sfeqi r4,0x21
438 l.sfeqi r4,0x37
440 l.sfeqi r4,0x35
447 lhs: l.lbs r5,0(r2)
452 l.andi r4,r4,0x7c
455 l.sw 0(r4),r5
457 lhz: l.lbz r5,0(r2)
462 l.andi r4,r4,0x7c
465 l.sw 0(r4),r5
467 lws: l.lbs r5,0(r2)
478 l.andi r4,r4,0x7c
481 l.sw 0(r4),r5
483 lwz: l.lbz r5,0(r2)
494 l.andi r4,r4,0x7c
497 l.sw 0(r4),r5
501 l.andi r4,r4,0x7c
503 l.lwz r5,0(r4)
507 l.sb 0(r2),r5
511 l.andi r4,r4,0x7c
513 l.lwz r5,0(r4)
521 l.sb 0(r2),r5
528 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
533 l.addi r3,r1,0 /* pt_regs */
538 /* ---[ 0x800: External interrupt exception ]---------------------------- */
544 l.sfeqi r4,0
549 l.addi r1,r1,-0x8
552 l.sw 0x0(r1),r3
554 l.sw 0x4(r1),r4
555 l.addi r1,r1,0x8
569 l.addi r3,r1,0
577 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
580 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
583 /* ---[ 0xb00: Range exception ]----------------------------------------- */
585 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
587 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
602 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
665 l.lwz r29,0(r29)
676 #if 0
693 #if 0
811 l.addi r3,r1,0
829 l.addi r3,r1,0
845 /* ---[ 0xd00: Floating Point exception ]-------------------------------- */
852 l.addi r3,r1,0 /* pt_regs */
857 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
863 l.addi r3,r1,0 /* pt_regs */
868 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
870 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
872 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
874 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
876 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
878 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
880 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
882 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
884 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
886 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
888 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
890 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
892 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
894 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
896 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
898 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
900 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
902 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
904 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
906 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
908 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
910 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
912 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
914 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
916 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
918 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
920 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
922 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
924 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
926 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
928 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
930 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
932 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
934 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
943 l.sfeqi r13,0
949 l.sfltsi r5,0
952 l.andi r5,r5,0
955 l.ori r3,r1,0 /* pt_regs */
957 l.sfeqi r11,0
960 l.sfltsi r11,0
996 l.sfeqi r3,0
1007 l.sfeqi r20,0
1075 .align 0x400
1098 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1196 l.addi r3,r1,0
1201 l.addi r3,r1,0
1223 l.lwz r29,0(r4)
1224 l.lwz r27,0(r5)
1225 l.sw 0(r4),r27
1226 l.sw 0(r5),r29