Lines Matching +full:supervisor +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
269 #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
295 #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
296 #define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
410 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
413 * Bit definitions for Debug Mode 1 register
448 #define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
453 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
512 * Bit definitions for Performance counters mode registers
516 #define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
517 #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
518 #define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
537 #define SPR_PMR_DME 0x00000010 /* Doze mode enable */
538 #define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
540 #define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
573 #define SPR_TTMR_M 0xc0000000 /* Tick mode */
580 #define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */