include/asm/spr_defs.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
141 #define SPR_VR_UVRP	0x00000040  /* Updated Version Registers Present */
154  * Bit definitions for the Unit Present Register
157 #define SPR_UPR_UP	   0x00000001  /* UPR present */
158 #define SPR_UPR_DCP	   0x00000002  /* Data cache present */
159 #define SPR_UPR_ICP	   0x00000004  /* Instruction cache present */
160 #define SPR_UPR_DMP	   0x00000008  /* Data MMU present */
161 #define SPR_UPR_IMP	   0x00000010  /* Instruction MMU present */
162 #define SPR_UPR_MP	   0x00000020  /* MAC present */
163 #define SPR_UPR_DUP	   0x00000040  /* Debug unit present */
164 #define SPR_UPR_PCUP	   0x00000080  /* Performance counters unit present */
165 #define SPR_UPR_PICP	   0x00000100  /* PIC present */
166 #define SPR_UPR_PMP	   0x00000200  /* Power management present */
167 #define SPR_UPR_TTP	   0x00000400  /* Tick timer present */
169 #define SPR_UPR_CUP	   0xff000000  /* Context units present */
217 #define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
269 #define SPR_DTLBTR_WBC	   0x00000004  /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
295 #define SPR_ITLBTR_WBC	   0x00000004  /* Write-Back Cache */
296 #define SPR_ITLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
387 #define SPR_DCR_DP	0x00000001  /* DVR/DCR present */
410 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
448 #define SPR_DMR1_ST	  0x00400000  /* Single-step trace*/
484 #define SPR_DSR_IE	0x00000080  /* Interrupt exception */
503 #define SPR_DRR_IE	0x00000080  /* Interrupt exception */
515 #define SPR_PCMR_CP	0x00000001  /* Counter present */
546 #define SPR_PICMR_IUM	0xfffffffc  /* Interrupt unmask */
552 #define SPR_PICPR_IPRIO	0xfffffffc  /* Interrupt priority */
558 #define SPR_PICSR_IS	0xffffffff  /* Interrupt status */
567 #define SPR_TTMR_IP	0x10000000  /* Interrupt Pending */
568 #define SPR_TTMR_IE	0x20000000  /* Interrupt Enable */