Lines Matching +full:supervisor +full:- +full:level
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
239 #define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
240 #define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
248 #define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
249 #define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
258 #define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
269 #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
284 #define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
295 #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
296 #define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
410 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
448 #define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
517 #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */