1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
29 #define SPRGROUP_IMMU	(2 << MAX_SPRS_PER_GRP_BITS)
43 #define SPR_CPUCFGR	(SPRGROUP_SYS + 2)
71 #define SPR_DTLBEIR	(SPRGROUP_DMMU + 2)
72 #define SPR_DTLBMR_BASE(WAY)	(SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)  argument
73 #define SPR_DTLBMR_LAST(WAY)	(SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)  argument
74 #define SPR_DTLBTR_BASE(WAY)	(SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)  argument
75 #define SPR_DTLBTR_LAST(WAY)	(SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)  argument
79 #define SPR_ITLBEIR	(SPRGROUP_IMMU + 2)
80 #define SPR_ITLBMR_BASE(WAY)	(SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)  argument
81 #define SPR_ITLBMR_LAST(WAY)	(SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)  argument
82 #define SPR_ITLBTR_BASE(WAY)	(SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)  argument
83 #define SPR_ITLBTR_LAST(WAY)	(SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)  argument
88 #define SPR_DCBFR	(SPRGROUP_DC + 2)
92 #define SPR_DCR_BASE(WAY)	(SPRGROUP_DC + 0x200 + (WAY) * 0x200)  argument
93 #define SPR_DCR_LAST(WAY)	(SPRGROUP_DC + 0x3ff + (WAY) * 0x200)  argument
98 #define SPR_ICBIR	(SPRGROUP_IC + 2)
100 #define SPR_ICR_BASE(WAY)	(SPRGROUP_IC + 0x200 + (WAY) * 0x200)  argument
101 #define SPR_ICR_LAST(WAY)	(SPRGROUP_IC + 0x3ff + (WAY) * 0x200)  argument
105 #define SPR_MACHI	(SPRGROUP_MAC + 2)
127 #define SPR_PICSR (SPRGROUP_PIC + 2)
148  * Bit definitions for the Version Register 2
202                                2 == n ? SPR_DCFGR_NDP2 : \
209 #define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
239 #define SPR_DMMUCR_P2S	   0x0000003e  /* Level 2 Page Size */
248 #define SPR_IMMUCR_P2S	   0x0000003e  /* Level 2 Page Size */
269 #define SPR_DTLBTR_WBC	   0x00000004  /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
295 #define SPR_ITLBTR_WBC	   0x00000004  /* Write-Back Cache */
296 #define SPR_ITLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
365 #define SPR_DMMUCFGR_NTS_OFF	2
381 #define SPR_IMMUCFGR_NTS_OFF	2
410 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
448 #define SPR_DMR1_ST	  0x00400000  /* Single-step trace*/
453  * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
459 #define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
596 #define FPCSR_RM_RIP (2<<1)