37 	MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
38 	MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
52 		.start = 0x1cd41ffc,
53 		.end   = 0x1cd41fff,
66 		.start = 0x18000000,
67 		.end   = 0x180fffff,
71 		.start = 0x1b000000,
72 		.end   = 0x1b000004,
76 		.start = 0x1ff00000,
77 		.end   = 0x1ff00020,
86 		.flags = 0x00
98 		.start = 0x19000000,
99 		.end   = 0x190fffff,
124 	return 0;  in snirm_setup_devinit()
137 #define PIC_CMD	   0x00
138 #define PIC_IMR	   0x01
145 #define MASTER_ICW4_DEFAULT	0x01
146 #define SLAVE_ICW4_DEFAULT	0x01
151 static unsigned int rm200_cached_irq_mask = 0xffff;
194 		writeb(0x0B, rm200_pic_master + PIC_CMD);  in sni_rm200_i8259A_irq_real()
196 		writeb(0x0A, rm200_pic_master + PIC_CMD);  in sni_rm200_i8259A_irq_real()
199 	writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */  in sni_rm200_i8259A_irq_real()
201 	writeb(0x0A, rm200_pic_slave + PIC_CMD);  in sni_rm200_i8259A_irq_real()
241 		writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);  in sni_rm200_mask_and_ack_8259A()
242 		writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);  in sni_rm200_mask_and_ack_8259A()
246 		writeb(0x60+irq, rm200_pic_master + PIC_CMD);  in sni_rm200_mask_and_ack_8259A()
302 	writeb(0x0C, rm200_pic_master + PIC_CMD);	/* prepare for poll */  in sni_rm200_i8259_irq()
309 		writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */  in sni_rm200_i8259_irq()
321 		writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */  in sni_rm200_i8259_irq()
322 		if (~readb(rm200_pic_master + PIC_ISR) & 0x80)  in sni_rm200_i8259_irq()
328 	return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;  in sni_rm200_i8259_irq()
337 	writeb(0xff, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
338 	writeb(0xff, rm200_pic_slave + PIC_IMR);  in sni_rm200_init_8259A()
340 	writeb(0x11, rm200_pic_master + PIC_CMD);  in sni_rm200_init_8259A()
341 	writeb(0, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
344 	writeb(0x11, rm200_pic_slave + PIC_CMD);  in sni_rm200_init_8259A()
362 	.start = 0x16000020,
363 	.end = 0x16000023,
369 	.start = 0x160000a0,
370 	.end = 0x160000a3,
380 	if (unlikely(irq < 0))  in sni_rm200_i8259A_irq_handler()
391 	rm200_pic_master = ioremap(0x16000020, 4);  in sni_rm200_i8259_irqs()
394 	rm200_pic_slave = ioremap(0x160000a0, 4);  in sni_rm200_i8259_irqs()
415 #define SNI_RM200_INT_STAT_REG	CKSEG1ADDR(0xbc000000)
416 #define SNI_RM200_INT_ENA_REG	CKSEG1ADDR(0xbc080000)
452 		mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f;  in sni_rm200_hwint()
453 		stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14;  in sni_rm200_hwint()
454 		irq = ffs(stat & mask & 0x1f);  in sni_rm200_hwint()
456 		if (likely(irq > 0))  in sni_rm200_hwint()
466 	* (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f;  in sni_rm200_irq_init()
475 	if (request_irq(SNI_RM200_INT_START + 0, sni_rm200_i8259A_irq_handler,  in sni_rm200_irq_init()
476 			0, "onboard ISA", NULL))  in sni_rm200_irq_init()
478 	if (request_irq(SNI_RM200_INT_START + 1, sni_isa_irq_handler, 0, "ISA",  in sni_rm200_irq_init()