mips/ralink/mt7621.c

1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pci.h>
18 #include <asm/smp-ops.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #include <asm/mach-ralink/mt7621.h>
35 	entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);  in pcibios_root_bridge_prepare()
38 		return -EINVAL;  in pcibios_root_bridge_prepare()
46 		mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;  in pcibios_root_bridge_prepare()
47 		WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);  in pcibios_root_bridge_prepare()
49 		write_gcr_reg1_base(entry->res->start);  in pcibios_root_bridge_prepare()
51 		pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",  in pcibios_root_bridge_prepare()
114 		return "MT7621";  in mt7621_get_soc_id()
149 		return -ENOMEM;  in mt7621_soc_dev_init()
151 	soc_dev_attr->soc_id = "mt7621";  in mt7621_soc_dev_init()
152 	soc_dev_attr->family = "Ralink";  in mt7621_soc_dev_init()
153 	soc_dev_attr->revision = mt7621_get_soc_revision();  in mt7621_soc_dev_init()
155 	soc_dev_attr->data = soc_info_ptr;  in mt7621_soc_dev_init()
192 		soc_info->compatible = "mediatek,mt7621-soc";  in prom_soc_init()
194 		panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",  in prom_soc_init()
199 	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,  in prom_soc_init()
205 	soc_info->mem_detect = mt7621_memory_detect;  in prom_soc_init()