Lines Matching +full:pm +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
20 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
22 #include <asm/mach-au1x00/au1000.h>
43 unsigned long pm[12]; member
94 ctx->wired_entry = read_c0_wired(); in alchemy_pci_wired_entry()
95 add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); in alchemy_pci_wired_entry()
96 ctx->last_elo0 = ctx->last_elo1 = ~0; in alchemy_pci_wired_entry()
99 static int config_access(unsigned char access_type, struct pci_bus *bus, in config_access() argument
102 struct alchemy_pci_context *ctx = bus->sysdata; in config_access()
110 return -1; in config_access()
114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; in config_access()
116 __raw_writel(r, ctx->regs + PCI_REG_STATCMD); in config_access()
119 /* Allow board vendors to implement their own off-chip IDSEL. in config_access()
122 if (ctx->board_pci_idsel(device, 1) == 0) { in config_access()
125 return -1; in config_access()
129 if (bus->number == 0) in config_access()
132 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); in config_access()
134 /* Setup the lower bits of the 36-bit address */ in config_access()
147 if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { in config_access()
148 mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, in config_access()
149 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); in config_access()
150 ctx->last_elo0 = entryLo0; in config_access()
151 ctx->last_elo1 = entryLo1; in config_access()
155 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); in config_access()
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); in config_access()
160 DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", in config_access()
161 access_type, bus->number, device, where, *data, offset); in config_access()
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); in config_access()
167 error = -1; in config_access()
168 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n", in config_access()
169 access_type, bus->number, device); in config_access()
171 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", in config_access()
175 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); in config_access()
178 error = -1; in config_access()
182 (void)ctx->board_pci_idsel(device, 0); in config_access()
188 static int read_config_byte(struct pci_bus *bus, unsigned int devfn, in read_config_byte() argument
192 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); in read_config_byte()
202 static int read_config_word(struct pci_bus *bus, unsigned int devfn, in read_config_word() argument
206 int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); in read_config_word()
214 static int read_config_dword(struct pci_bus *bus, unsigned int devfn, in read_config_dword() argument
217 return config_access(PCI_ACCESS_READ, bus, devfn, where, val); in read_config_dword()
220 static int write_config_byte(struct pci_bus *bus, unsigned int devfn, in write_config_byte() argument
225 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) in write_config_byte()
226 return -1; in write_config_byte()
231 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) in write_config_byte()
232 return -1; in write_config_byte()
237 static int write_config_word(struct pci_bus *bus, unsigned int devfn, in write_config_word() argument
242 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) in write_config_word()
243 return -1; in write_config_word()
248 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) in write_config_word()
249 return -1; in write_config_word()
254 static int write_config_dword(struct pci_bus *bus, unsigned int devfn, in write_config_dword() argument
257 return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); in write_config_dword()
260 static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, in alchemy_pci_read() argument
266 int rc = read_config_byte(bus, devfn, where, &_val); in alchemy_pci_read()
273 int rc = read_config_word(bus, devfn, where, &_val); in alchemy_pci_read()
279 return read_config_dword(bus, devfn, where, val); in alchemy_pci_read()
283 static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, in alchemy_pci_write() argument
288 return write_config_byte(bus, devfn, where, (u8) val); in alchemy_pci_write()
290 return write_config_word(bus, devfn, where, (u16) val); in alchemy_pci_write()
292 return write_config_dword(bus, devfn, where, val); in alchemy_pci_write()
313 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); in alchemy_pci_suspend()
314 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; in alchemy_pci_suspend()
315 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_suspend()
316 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_suspend()
317 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_suspend()
318 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_suspend()
319 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_suspend()
320 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); in alchemy_pci_suspend()
321 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); in alchemy_pci_suspend()
322 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); in alchemy_pci_suspend()
323 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); in alchemy_pci_suspend()
324 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); in alchemy_pci_suspend()
335 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); in alchemy_pci_resume()
336 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_resume()
337 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_resume()
338 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_resume()
339 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_resume()
340 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_resume()
341 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); in alchemy_pci_resume()
342 __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); in alchemy_pci_resume()
343 __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); in alchemy_pci_resume()
344 __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); in alchemy_pci_resume()
345 __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); in alchemy_pci_resume()
347 __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); in alchemy_pci_resume()
353 ctx->wired_entry = 8191; /* impossibly high value */ in alchemy_pci_resume()
364 struct alchemy_pci_platdata *pd = pdev->dev.platform_data; in alchemy_pci_probe()
374 dev_err(&pdev->dev, "need platform data for PCI setup\n"); in alchemy_pci_probe()
375 ret = -ENODEV; in alchemy_pci_probe()
381 dev_err(&pdev->dev, "no memory for pcictl context\n"); in alchemy_pci_probe()
382 ret = -ENOMEM; in alchemy_pci_probe()
388 dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); in alchemy_pci_probe()
389 ret = -ENODEV; in alchemy_pci_probe()
393 if (!request_mem_region(r->start, resource_size(r), pdev->name)) { in alchemy_pci_probe()
394 dev_err(&pdev->dev, "cannot claim pci regs\n"); in alchemy_pci_probe()
395 ret = -ENODEV; in alchemy_pci_probe()
399 c = clk_get(&pdev->dev, "pci_clko"); in alchemy_pci_probe()
401 dev_err(&pdev->dev, "unable to find PCI clock\n"); in alchemy_pci_probe()
408 dev_err(&pdev->dev, "cannot enable PCI clock\n"); in alchemy_pci_probe()
412 ctx->regs = ioremap(r->start, resource_size(r)); in alchemy_pci_probe()
413 if (!ctx->regs) { in alchemy_pci_probe()
414 dev_err(&pdev->dev, "cannot map pci regs\n"); in alchemy_pci_probe()
415 ret = -ENODEV; in alchemy_pci_probe()
425 dev_err(&pdev->dev, "cannot remap pci io space\n"); in alchemy_pci_probe()
426 ret = -ENODEV; in alchemy_pci_probe()
429 ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; in alchemy_pci_probe()
434 val = __raw_readl(ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()
436 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()
438 dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); in alchemy_pci_probe()
441 if (pd->board_map_irq) in alchemy_pci_probe()
442 ctx->board_map_irq = pd->board_map_irq; in alchemy_pci_probe()
444 if (pd->board_pci_idsel) in alchemy_pci_probe()
445 ctx->board_pci_idsel = pd->board_pci_idsel; in alchemy_pci_probe()
447 ctx->board_pci_idsel = alchemy_pci_def_idsel; in alchemy_pci_probe()
450 ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; in alchemy_pci_probe()
451 ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; in alchemy_pci_probe()
452 ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; in alchemy_pci_probe()
460 ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); in alchemy_pci_probe()
461 if (!ctx->pci_cfg_vm) { in alchemy_pci_probe()
462 dev_err(&pdev->dev, "unable to get vm area\n"); in alchemy_pci_probe()
463 ret = -ENOMEM; in alchemy_pci_probe()
466 ctx->wired_entry = 8191; /* impossibly high value */ in alchemy_pci_probe()
469 set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); in alchemy_pci_probe()
472 val = __raw_readl(ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()
473 val &= ~pd->pci_cfg_clr; in alchemy_pci_probe()
474 val |= pd->pci_cfg_set; in alchemy_pci_probe()
476 __raw_writel(val, ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()
482 register_pci_controller(&ctx->alchemy_pci_ctrl); in alchemy_pci_probe()
484 dev_info(&pdev->dev, "PCI controller at %ld MHz\n", in alchemy_pci_probe()
492 iounmap(ctx->regs); in alchemy_pci_probe()
498 release_mem_region(r->start, resource_size(r)); in alchemy_pci_probe()
508 .name = "alchemy-pci",
527 struct alchemy_pci_context *ctx = dev->sysdata; in pcibios_map_irq()
528 if (ctx && ctx->board_map_irq) in pcibios_map_irq()
529 return ctx->board_map_irq(dev, slot, pin); in pcibios_map_irq()
530 return -1; in pcibios_map_irq()