Lines Matching full:ir
849 mips_instruction ir) in cop1_cfc() argument
854 switch (MIPSInst_RD(ir)) { in cop1_cfc()
858 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
868 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
876 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
887 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
898 if (MIPSInst_RT(ir)) in cop1_cfc()
899 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
906 mips_instruction ir) in cop1_ctc() argument
912 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
915 value = xcp->regs[MIPSInst_RT(ir)]; in cop1_ctc()
917 switch (MIPSInst_RD(ir)) { in cop1_ctc()
920 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
931 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
942 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
951 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
976 mips_instruction ir; in cop1Emulate() local
1016 ir = dec_insn.next_insn; /* process delay slot instr */ in cop1Emulate()
1019 ir = dec_insn.insn; /* process current instr */ in cop1Emulate()
1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) in cop1Emulate()
1048 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1051 MIPSInst_SIMM(ir)); in cop1Emulate()
1064 DITOREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1069 MIPSInst_SIMM(ir)); in cop1Emulate()
1071 DIFROMREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1086 MIPSInst_SIMM(ir)); in cop1Emulate()
1098 SITOREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1103 MIPSInst_SIMM(ir)); in cop1Emulate()
1105 SIFROMREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1119 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1125 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1127 MIPSInst_RD(ir)); in cop1Emulate()
1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1144 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1146 MIPSInst_RD(ir)); in cop1Emulate()
1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1160 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1162 MIPSInst_RD(ir)); in cop1Emulate()
1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1173 cop1_cfc(xcp, ctx, ir); in cop1Emulate()
1178 cop1_ctc(xcp, ctx, ir); in cop1Emulate()
1191 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)]; in cop1Emulate()
1193 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1210 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1216 switch (MIPSInst_RT(ir) & 3) { in cop1Emulate()
1248 contpc = MIPSInst_SIMM(ir); in cop1Emulate()
1249 ir = dec_insn.next_insn; in cop1Emulate()
1255 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { in cop1Emulate()
1265 ir = (ir & (~0xffff)) | MM_NOP16; in cop1Emulate()
1271 sig = mips_dsemul(xcp, ir, in cop1Emulate()
1286 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1309 switch (MIPSInst_FUNC(ir)) { in cop1Emulate()
1327 sig = mips_dsemul(xcp, ir, bcpc, contpc); in cop1Emulate()
1349 if (!(MIPSInst_RS(ir) & 0x10)) in cop1Emulate()
1353 sig = fpu_emu(xcp, ctx, ir); in cop1Emulate()
1363 sig = fpux_emu(xcp, ctx, ir, fault_addr); in cop1Emulate()
1372 if (MIPSInst_FUNC(ir) != movc_op) in cop1Emulate()
1374 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1375 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()
1376 xcp->regs[MIPSInst_RD(ir)] = in cop1Emulate()
1377 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()
1464 mips_instruction ir, void __user **fault_addr) in fpux_emu() argument
1470 switch (MIPSInst_FMA_FFMT(ir)) { in fpux_emu()
1478 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1480 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1481 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1494 SITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1498 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1499 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1503 SIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1542 SPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1543 SPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1544 SPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1546 SPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1587 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1589 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1590 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1603 DITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1607 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1608 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1611 DIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1650 DPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1651 DPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1652 DPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1654 DPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1664 if (MIPSInst_FUNC(ir) != pfetch_op) in fpux_emu()
1683 mips_instruction ir) in fpu_emu() argument
1699 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { in fpu_emu()
1707 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
1760 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
1762 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
1764 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1771 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1773 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1780 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1782 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1790 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1794 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1802 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1804 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1816 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1817 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1818 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1830 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1831 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1832 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1844 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1856 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1869 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1870 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1882 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1883 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1895 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1896 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1908 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1909 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1927 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1932 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1933 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1938 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1970 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1977 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1989 if (MIPSInst_FUNC(ir) == fceil_op) in fpu_emu()
1991 if (MIPSInst_FUNC(ir) == ffloor_op) in fpu_emu()
1993 if (MIPSInst_FUNC(ir) == fround_op) in fpu_emu()
1995 if (MIPSInst_FUNC(ir) == ftrunc_op) in fpu_emu()
1999 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2000 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2011 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2013 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
2015 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
2023 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2035 if (MIPSInst_FUNC(ir) == fceill_op) in fpu_emu()
2037 if (MIPSInst_FUNC(ir) == ffloorl_op) in fpu_emu()
2039 if (MIPSInst_FUNC(ir) == froundl_op) in fpu_emu()
2041 if (MIPSInst_FUNC(ir) == ftruncl_op) in fpu_emu()
2045 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2046 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2053 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
2057 cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
2058 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2059 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2083 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2133 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
2135 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
2137 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2143 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
2145 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2151 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
2153 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2161 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2165 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2173 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2175 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2187 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2188 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2189 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2201 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2202 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2203 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2215 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2227 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2240 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2241 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2253 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2254 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2266 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2267 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2279 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2280 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2298 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2303 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2304 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2309 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2318 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2328 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2340 if (MIPSInst_FUNC(ir) == fceil_op) in fpu_emu()
2342 if (MIPSInst_FUNC(ir) == ffloor_op) in fpu_emu()
2344 if (MIPSInst_FUNC(ir) == fround_op) in fpu_emu()
2346 if (MIPSInst_FUNC(ir) == ftrunc_op) in fpu_emu()
2350 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2351 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2362 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2364 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2366 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2374 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2386 if (MIPSInst_FUNC(ir) == fceill_op) in fpu_emu()
2388 if (MIPSInst_FUNC(ir) == ffloorl_op) in fpu_emu()
2390 if (MIPSInst_FUNC(ir) == froundl_op) in fpu_emu()
2392 if (MIPSInst_FUNC(ir) == ftruncl_op) in fpu_emu()
2396 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2397 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2404 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
2408 cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
2409 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2410 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2434 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2438 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2445 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2455 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; in fpu_emu()
2456 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; in fpu_emu()
2461 (MIPSInst_FUNC(ir) & 0x20)) in fpu_emu()
2465 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2506 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2554 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2555 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2558 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2599 DIFROMREG(bits, MIPSInst_FS(ir)); in fpu_emu()
2601 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2616 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; in fpu_emu()
2617 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; in fpu_emu()
2621 (MIPSInst_FUNC(ir) & 0x20)) in fpu_emu()
2625 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2666 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2714 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2715 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2718 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2777 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; in fpu_emu()
2787 DPTOREG(rv.d, MIPSInst_FD(ir)); in fpu_emu()
2790 SPTOREG(rv.s, MIPSInst_FD(ir)); in fpu_emu()
2793 SITOREG(rv.w, MIPSInst_FD(ir)); in fpu_emu()
2799 DITOREG(rv.l, MIPSInst_FD(ir)); in fpu_emu()