Lines Matching +full:64 +full:bit
337 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
338 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
339 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
340 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
341 * instructions on 32-bit kernels. in emulate_load_store_insn()
354 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
360 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
361 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
362 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
363 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
364 * instructions on 32-bit kernels. in emulate_load_store_insn()
377 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
415 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
416 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
417 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
418 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
419 * instructions on 32-bit kernels. in emulate_load_store_insn()
432 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
609 /* Recode table from 16-bit register notation to 32-bit GPR. */
612 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1120 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1121 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1122 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1123 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1124 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1136 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1142 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1143 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1144 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1145 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1146 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1158 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1184 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1185 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1186 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1187 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1188 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1200 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1386 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1387 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1388 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1389 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1390 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1403 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1410 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1411 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1412 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1413 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1414 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1427 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1458 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1459 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1460 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1461 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1462 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1475 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1529 * virtual user address and 64bit maximum virtual user address in do_ade()
1564 * 16-bit mode? in do_ade()