50 #define RESET_FROM_KSEG0		0x80080800
51 #define RESET_FROM_KSEG1		0xa0080800
68 /* SW interrupts 0,1 are used for interprocessor signaling */
69 #define IPI0_IRQ			(MIPS_CPU_IRQ_BASE + 0)
73 #define ACTION_CLR_IPI(cpu, ipi)	(0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
74 #define ACTION_SET_IPI(cpu, ipi)	(0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
75 #define ACTION_BOOT_THREAD(cpu)		(0x08 | CPUNUM(cpu, 0))
79 	int i, cpu = 1, boot_cpu = 0;  in bmips_smp_setup()
86 		clear_c0_brcm_cmt_ctrl(0x30);  in bmips_smp_setup()
89 		set_c0_brcm_config_0(0x30000);  in bmips_smp_setup()
95 		 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other  in bmips_smp_setup()
97 		 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output  in bmips_smp_setup()
100 		if (boot_cpu == 0)  in bmips_smp_setup()
101 			cpu_hw_intr = 0x02;  in bmips_smp_setup()
103 			cpu_hw_intr = 0x1d;  in bmips_smp_setup()
105 		change_c0_brcm_cmt_intr(0xf8018000,  in bmips_smp_setup()
106 					(cpu_hw_intr << 27) | (0x03 << 15));  in bmips_smp_setup()
114 		set_c0_brcm_config(0x03 << 22);  in bmips_smp_setup()
116 		/* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */  in bmips_smp_setup()
117 		change_c0_brcm_mode(0x1f << 27, 0x02 << 27);  in bmips_smp_setup()
120 		max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;  in bmips_smp_setup()
123 		for (i = 0; i < max_cpus; i++) {  in bmips_smp_setup()
124 			write_c0_brcm_action(ACTION_CLR_IPI(i, 0));  in bmips_smp_setup()
141 		__cpu_number_map[boot_cpu] = 0;  in bmips_smp_setup()
142 		__cpu_logical_map[0] = boot_cpu;  in bmips_smp_setup()
144 		for (i = 0; i < max_cpus; i++) {  in bmips_smp_setup()
154 		__cpu_number_map[0] = boot_cpu;  in bmips_smp_setup()
155 		__cpu_logical_map[0] = 0;  in bmips_smp_setup()
156 		set_cpu_possible(0, 1);  in bmips_smp_setup()
157 		set_cpu_present(0, 1);  in bmips_smp_setup()
221 			bmips43xx_send_ipi_single(cpu, 0);  in bmips_boot_secondary()
224 			bmips5000_send_ipi_single(cpu, 0);  in bmips_boot_secondary()
235 				set_c0_brcm_cmt_ctrl(0x01);  in bmips_boot_secondary()
244 	return 0;  in bmips_boot_secondary()
260 		write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));  in bmips_init_secondary()
300 	if (action == 0)  in bmips5000_ipi_interrupt()
348 	per_cpu(ipi_action_mask, cpu) = 0;  in bmips43xx_ipi_interrupt()
383 	local_flush_icache_range(0, ~0);  in bmips_cpu_disable()
385 	return 0;  in bmips_cpu_disable()
398 	_dma_cache_wback_inv(0, ~0);  in play_dead()
491 	int shift = info->cpu & 0x01 ? 16 : 0;  in bmips_set_reset_vec_remote()
492 	u32 mask = ~(0xffff << shift), val = info->val >> 16;  in bmips_set_reset_vec_remote()
495 	if (smp_processor_id() > 0) {  in bmips_set_reset_vec_remote()
496 		smp_call_function_single(0, &bmips_set_reset_vec_remote,  in bmips_set_reset_vec_remote()
499 		if (info->cpu & 0x02) {  in bmips_set_reset_vec_remote()
501 			bmips_write_zscm_reg(0xa0, (val << 16) | val);  in bmips_set_reset_vec_remote()
502 			bmips_read_zscm_reg(0xa0);  in bmips_set_reset_vec_remote()
523 		if (cpu == 0)  in bmips_set_reset_vec()
546 		 * the relocated BEV=1, IV=0 general exception vector @  in bmips_ebase_setup()
547 		 * 0xa000_0380.  in bmips_ebase_setup()
554 			&bmips_smp_int_vec, 0x80);  in bmips_ebase_setup()
560 		 * 0x8000_0000: reset/NMI (initially in kseg1)  in bmips_ebase_setup()
561 		 * 0x8000_0400: normal vectors  in bmips_ebase_setup()
563 		new_ebase = 0x80000400;  in bmips_ebase_setup()
564 		bmips_set_reset_vec(0, RESET_FROM_KSEG0);  in bmips_ebase_setup()
568 		 * 0x8000_0000: reset/NMI (initially in kseg1)  in bmips_ebase_setup()
569 		 * 0x8000_1000: normal vectors  in bmips_ebase_setup()
571 		new_ebase = 0x80001000;  in bmips_ebase_setup()
572 		bmips_set_reset_vec(0, RESET_FROM_KSEG0);  in bmips_ebase_setup()
612 		__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
616 		__raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
620 		__raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);  in bmips_cpu_setup()
632 		__raw_writel(cfg | 0xf, cbr + rac_addr);  in bmips_cpu_setup()
637 		__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
644 		case 0x2a040:  in bmips_cpu_setup()
645 		case 0x2a042:  in bmips_cpu_setup()
646 		case 0x2a044:  in bmips_cpu_setup()
647 		case 0x2a060:  in bmips_cpu_setup()
649 			__raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);  in bmips_cpu_setup()
668 		"	li	$8, 0x5a455048\n"  in bmips_cpu_setup()
669 		"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */  in bmips_cpu_setup()
670 		"	.word	0x4008b008\n"	/* mfc0	t0, $22, 8 */  in bmips_cpu_setup()
671 		"	li	$9, 0x00008000\n"  in bmips_cpu_setup()
673 		"	.word	0x4088b008\n"	/* mtc0	t0, $22, 8 */  in bmips_cpu_setup()
675 		"	li	$8, 0x0\n"  in bmips_cpu_setup()
676 		"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */  in bmips_cpu_setup()
685 		"	li	$8, 0x5a455048\n"  in bmips_cpu_setup()
686 		"	.word	0x4088b00f\n"	/* mtc0 $8, $22, 15 */  in bmips_cpu_setup()
688 		"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */  in bmips_cpu_setup()
689 		"	lui	$9, 0x0100\n"  in bmips_cpu_setup()
691 		"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */  in bmips_cpu_setup()