3  * MIPS idle loop and WAIT instruction support.
23  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
24  * the implementation of the "wait" feature differs between CPU families. This
25  * points to the function that implements CPU specific wait.
26  * The wait instruction stops the pipeline and reduces the power consumption of
58 		"	wait			\n"  in r4k_wait_irqoff()
64  * have any pending stores when the WAIT instruction is executed.
76 		"	wait						\n"  in rm7k_wait_irqoff()
82  * Au1 'wait' is only useful when the 32kHz counter is used as timer,
97 	"	wait				\n"  in au1k_wait()
124 		printk("Wait instruction disabled.\n");  in check_wait()
130 	 * wait instruction, and thus that it is safe for us to use  in check_wait()
187 		 * Incoming Fast Debug Channel (FDC) data during a wait  in check_wait()
188 		 * instruction causes the wait never to resume, even if an  in check_wait()
189 		 * interrupt is received. Avoid using wait at all if FDC data is  in check_wait()
223 		 * WAIT on Rev1.0 has E1, E2, E3 and E16.  in check_wait()
224 		 * WAIT on Rev2.0 and Rev3.0 has E16.  in check_wait()
225 		 * Rev3.1 WAIT is nop, why bother  in check_wait()
232 		 * rate while in WAIT mode.  So we basically have the choice  in check_wait()
234 		 * the WAIT instruction.  Until more details are known,  in check_wait()
235 		 * disable the use of WAIT for 20Kc entirely.  in check_wait()