Lines Matching +full:loongson +full:- +full:2 +full:k
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1994 - 2006 Ralf Baechle
19 #include <asm/cpu-features.h>
20 #include <asm/cpu-type.h>
27 #include <asm/pgtable-bits.h>
32 #include "fpu-probe.h"
34 #include <asm/mach-loongson64/cpucfg-emul.h>
131 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * in ftlb_disable()
147 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; in cpu_set_mt_per_tc_perf()
161 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) in check_errata()
213 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); in cpu_probe_vmbits()
221 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; in set_isa()
225 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; in set_isa()
229 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; in set_isa()
233 c->isa_level |= MIPS_CPU_ISA_V; in set_isa()
237 c->isa_level |= MIPS_CPU_ISA_IV; in set_isa()
241 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; in set_isa()
247 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; in set_isa()
251 c->isa_level |= MIPS_CPU_ISA_M32R6; in set_isa()
256 c->isa_level |= MIPS_CPU_ISA_M32R5; in set_isa()
260 c->isa_level |= MIPS_CPU_ISA_M32R2; in set_isa()
264 c->isa_level |= MIPS_CPU_ISA_M32R1; in set_isa()
268 c->isa_level |= MIPS_CPU_ISA_II; in set_isa()
280 unsigned int probability = c->tlbsize / c->tlbsizevtlb; in calculate_ftlb_probability()
286 * 2 = 7:1: As above with 7:1 ratio. in calculate_ftlb_probability()
294 return 2; in calculate_ftlb_probability()
308 switch (c->cputype) { in set_ftlb_enable()
339 /* Loongson-3 cores use Config6 to enable the FTLB */ in set_ftlb_enable()
363 * It's implementation dependent what type of write-merge is supported in mm_config()
366 * write-through caching unsupported. In this case just ignore the in mm_config()
369 switch (c->cputype) { in mm_config()
375 c->options |= MIPS_CPU_MM_FULL; in mm_config()
393 c->options |= MIPS_CPU_MM_SYSAD; in mm_config()
395 c->options |= MIPS_CPU_MM_FULL; in mm_config()
413 c->options |= MIPS_CPU_TLB; in decode_config0()
415 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; in decode_config0()
427 case 2: in decode_config0()
434 case 2: in decode_config0()
442 case 2: in decode_config0()
466 c->ases |= MIPS_ASE_MDMX; in decode_config1()
468 c->options |= MIPS_CPU_PERF; in decode_config1()
470 c->options |= MIPS_CPU_WATCH; in decode_config1()
472 c->ases |= MIPS_ASE_MIPS16; in decode_config1()
474 c->options |= MIPS_CPU_EJTAG; in decode_config1()
476 c->options |= MIPS_CPU_FPU; in decode_config1()
477 c->options |= MIPS_CPU_32FPR; in decode_config1()
480 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; in decode_config1()
481 c->tlbsizevtlb = c->tlbsize; in decode_config1()
482 c->tlbsizeftlbsets = 0; in decode_config1()
495 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; in decode_config2()
507 c->ases |= MIPS_ASE_SMARTMIPS; in decode_config3()
508 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; in decode_config3()
511 c->options |= MIPS_CPU_RIXI; in decode_config3()
513 c->options |= MIPS_CPU_CTXTC; in decode_config3()
515 c->ases |= MIPS_ASE_DSP; in decode_config3()
517 c->ases |= MIPS_ASE_DSP2P; in decode_config3()
519 c->ases |= MIPS_ASE_DSP3; in decode_config3()
522 c->options |= MIPS_CPU_VINT; in decode_config3()
524 c->options |= MIPS_CPU_VEIC; in decode_config3()
526 c->options |= MIPS_CPU_LPA; in decode_config3()
528 c->ases |= MIPS_ASE_MIPSMT; in decode_config3()
530 c->options |= MIPS_CPU_ULRI; in decode_config3()
532 c->options |= MIPS_CPU_MICROMIPS; in decode_config3()
534 c->ases |= MIPS_ASE_VZ; in decode_config3()
536 c->options |= MIPS_CPU_SEGMENTS; in decode_config3()
538 c->options |= MIPS_CPU_BADINSTR; in decode_config3()
540 c->options |= MIPS_CPU_BADINSTRP; in decode_config3()
542 c->ases |= MIPS_ASE_MSA; in decode_config3()
544 c->htw_seq = 0; in decode_config3()
545 c->options |= MIPS_CPU_HTW; in decode_config3()
548 c->options |= MIPS_CPU_CDMM; in decode_config3()
550 c->options |= MIPS_CPU_SP; in decode_config3()
566 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) in decode_config4()
567 c->options |= MIPS_CPU_TLBINV; in decode_config4()
583 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; in decode_config4()
584 c->tlbsizevtlb = c->tlbsize; in decode_config4()
587 c->tlbsizevtlb += in decode_config4()
590 c->tlbsize = c->tlbsizevtlb; in decode_config4()
610 c->tlbsizeftlbsets = 1 << in decode_config4()
613 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> in decode_config4()
614 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; in decode_config4()
615 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; in decode_config4()
621 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) in decode_config4()
657 c->options |= MIPS_CPU_EVA; in decode_config5()
659 c->options |= MIPS_CPU_MAAR; in decode_config5()
661 c->options |= MIPS_CPU_RW_LLB; in decode_config5()
663 c->options |= MIPS_CPU_MVH; in decode_config5()
665 c->options |= MIPS_CPU_VP; in decode_config5()
667 c->ases |= MIPS_ASE_MIPS16E2; in decode_config5()
679 c->options |= MIPS_CPU_MMID; in decode_config5()
700 * bitmap - that's too big in most cases. in decode_config5()
706 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { in decode_config5()
709 asid_mask = GENMASK(max_mmid_width - 1, 0); in decode_config5()
724 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | in decode_configs()
727 c->scache.flags = MIPS_CACHE_NOT_PRESENT; in decode_configs()
755 c->options |= MIPS_CPU_EBASE_WG; in decode_configs()
762 * On pre-r6 cores, this may well clobber the upper bits in decode_configs()
764 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. in decode_configs()
774 c->options |= MIPS_CPU_EBASE_WG; in decode_configs()
791 core >>= fls(core_nvpes()) - 1; in decode_configs()
832 c->guest.conf |= BIT(1); in decode_guest_config0()
845 c->guest.options |= MIPS_CPU_FPU; in decode_guest_config1()
847 c->guest.options_dyn |= MIPS_CPU_FPU; in decode_guest_config1()
850 c->guest.options |= MIPS_CPU_WATCH; in decode_guest_config1()
852 c->guest.options_dyn |= MIPS_CPU_WATCH; in decode_guest_config1()
855 c->guest.options |= MIPS_CPU_PERF; in decode_guest_config1()
857 c->guest.options_dyn |= MIPS_CPU_PERF; in decode_guest_config1()
860 c->guest.conf |= BIT(2); in decode_guest_config1()
871 c->guest.conf |= BIT(3); in decode_guest_config2()
884 c->guest.options |= MIPS_CPU_CTXTC; in decode_guest_config3()
886 c->guest.options_dyn |= MIPS_CPU_CTXTC; in decode_guest_config3()
889 c->guest.options |= MIPS_CPU_HTW; in decode_guest_config3()
892 c->guest.options |= MIPS_CPU_ULRI; in decode_guest_config3()
895 c->guest.options |= MIPS_CPU_SEGMENTS; in decode_guest_config3()
898 c->guest.options |= MIPS_CPU_BADINSTR; in decode_guest_config3()
900 c->guest.options |= MIPS_CPU_BADINSTRP; in decode_guest_config3()
903 c->guest.ases |= MIPS_ASE_MSA; in decode_guest_config3()
905 c->guest.ases_dyn |= MIPS_ASE_MSA; in decode_guest_config3()
908 c->guest.conf |= BIT(4); in decode_guest_config3()
919 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) in decode_guest_config4()
923 c->guest.conf |= BIT(5); in decode_guest_config4()
935 c->guest.options |= MIPS_CPU_MAAR; in decode_guest_config5()
937 c->guest.options_dyn |= MIPS_CPU_MAAR; in decode_guest_config5()
940 c->guest.options |= MIPS_CPU_RW_LLB; in decode_guest_config5()
943 c->guest.options |= MIPS_CPU_MVH; in decode_guest_config5()
946 c->guest.conf |= BIT(6); in decode_guest_config5()
974 c->options |= MIPS_CPU_GUESTCTL0EXT; in cpu_probe_guestctl0()
976 c->options |= MIPS_CPU_GUESTCTL1; in cpu_probe_guestctl0()
978 c->options |= MIPS_CPU_GUESTCTL2; in cpu_probe_guestctl0()
980 c->options |= MIPS_CPU_GUESTID; in cpu_probe_guestctl0()
996 c->options |= MIPS_CPU_DRG; in cpu_probe_guestctl0()
1007 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) in cpu_probe_guestctl1()
1018 c->gtoffset_mask = read_c0_gtoffset(); in cpu_probe_gtoffset()
1038 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_legacy()
1040 c->cputype = CPU_R2000; in cpu_probe_legacy()
1042 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; in cpu_probe_legacy()
1043 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | in cpu_probe_legacy()
1046 c->options |= MIPS_CPU_FPU; in cpu_probe_legacy()
1047 c->tlbsize = 64; in cpu_probe_legacy()
1050 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { in cpu_probe_legacy()
1052 c->cputype = CPU_R3081E; in cpu_probe_legacy()
1055 c->cputype = CPU_R3000A; in cpu_probe_legacy()
1059 c->cputype = CPU_R3000; in cpu_probe_legacy()
1062 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; in cpu_probe_legacy()
1063 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | in cpu_probe_legacy()
1066 c->options |= MIPS_CPU_FPU; in cpu_probe_legacy()
1067 c->tlbsize = 64; in cpu_probe_legacy()
1071 if ((c->processor_id & PRID_REV_MASK) >= in cpu_probe_legacy()
1073 c->cputype = CPU_R4400PC; in cpu_probe_legacy()
1076 c->cputype = CPU_R4000PC; in cpu_probe_legacy()
1100 if ((c->processor_id & PRID_REV_MASK) >= in cpu_probe_legacy()
1102 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; in cpu_probe_legacy()
1105 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; in cpu_probe_legacy()
1111 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1112 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1115 c->tlbsize = 48; in cpu_probe_legacy()
1118 c->cputype = CPU_R4300; in cpu_probe_legacy()
1121 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1122 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1124 c->tlbsize = 32; in cpu_probe_legacy()
1127 c->cputype = CPU_R4600; in cpu_probe_legacy()
1130 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1131 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1133 c->tlbsize = 48; in cpu_probe_legacy()
1143 c->cputype = CPU_R4650; in cpu_probe_legacy()
1146 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1147 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; in cpu_probe_legacy()
1148 c->tlbsize = 48; in cpu_probe_legacy()
1152 c->cputype = CPU_R4700; in cpu_probe_legacy()
1155 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1156 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1158 c->tlbsize = 48; in cpu_probe_legacy()
1161 c->cputype = CPU_TX49XX; in cpu_probe_legacy()
1164 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1165 c->options = R4K_OPTS | MIPS_CPU_LLSC; in cpu_probe_legacy()
1166 if (!(c->processor_id & 0x08)) in cpu_probe_legacy()
1167 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; in cpu_probe_legacy()
1168 c->tlbsize = 48; in cpu_probe_legacy()
1171 c->cputype = CPU_R5000; in cpu_probe_legacy()
1174 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1176 c->tlbsize = 48; in cpu_probe_legacy()
1179 c->cputype = CPU_R5500; in cpu_probe_legacy()
1182 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1184 c->tlbsize = 48; in cpu_probe_legacy()
1187 c->cputype = CPU_NEVADA; in cpu_probe_legacy()
1190 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1192 c->tlbsize = 48; in cpu_probe_legacy()
1195 c->cputype = CPU_RM7000; in cpu_probe_legacy()
1198 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1208 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; in cpu_probe_legacy()
1211 c->cputype = CPU_R10000; in cpu_probe_legacy()
1214 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | in cpu_probe_legacy()
1218 c->tlbsize = 64; in cpu_probe_legacy()
1221 c->cputype = CPU_R12000; in cpu_probe_legacy()
1224 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | in cpu_probe_legacy()
1228 c->tlbsize = 64; in cpu_probe_legacy()
1232 if (((c->processor_id >> 4) & 0x0f) > 2) { in cpu_probe_legacy()
1233 c->cputype = CPU_R16000; in cpu_probe_legacy()
1236 c->cputype = CPU_R14000; in cpu_probe_legacy()
1240 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | in cpu_probe_legacy()
1244 c->tlbsize = 64; in cpu_probe_legacy()
1247 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ in cpu_probe_legacy()
1248 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_legacy()
1250 c->cputype = CPU_LOONGSON2EF; in cpu_probe_legacy()
1251 __cpu_name[cpu] = "ICT Loongson-2"; in cpu_probe_legacy()
1254 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1257 c->cputype = CPU_LOONGSON2EF; in cpu_probe_legacy()
1258 __cpu_name[cpu] = "ICT Loongson-2"; in cpu_probe_legacy()
1261 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1264 c->cputype = CPU_LOONGSON64; in cpu_probe_legacy()
1265 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_legacy()
1268 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | in cpu_probe_legacy()
1273 c->cputype = CPU_LOONGSON64; in cpu_probe_legacy()
1274 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_legacy()
1277 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | in cpu_probe_legacy()
1282 c->options = R4K_OPTS | in cpu_probe_legacy()
1285 c->tlbsize = 64; in cpu_probe_legacy()
1287 c->writecombine = _CACHE_UNCACHED_ACCELERATED; in cpu_probe_legacy()
1289 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ in cpu_probe_legacy()
1292 c->cputype = CPU_LOONGSON32; in cpu_probe_legacy()
1294 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_legacy()
1296 __cpu_name[cpu] = "Loongson 1B"; in cpu_probe_legacy()
1306 c->writecombine = _CACHE_UNCACHED_ACCELERATED; in cpu_probe_mips()
1307 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_mips()
1309 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1310 c->cputype = CPU_QEMU_GENERIC; in cpu_probe_mips()
1314 c->cputype = CPU_4KC; in cpu_probe_mips()
1315 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1320 c->cputype = CPU_4KEC; in cpu_probe_mips()
1321 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1326 c->cputype = CPU_4KSC; in cpu_probe_mips()
1327 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1331 c->cputype = CPU_5KC; in cpu_probe_mips()
1332 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1336 c->cputype = CPU_5KE; in cpu_probe_mips()
1337 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1341 c->cputype = CPU_20KC; in cpu_probe_mips()
1342 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1346 c->cputype = CPU_24K; in cpu_probe_mips()
1347 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1351 c->cputype = CPU_24K; in cpu_probe_mips()
1352 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1356 c->cputype = CPU_25KF; in cpu_probe_mips()
1357 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1361 c->cputype = CPU_34K; in cpu_probe_mips()
1362 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1367 c->cputype = CPU_74K; in cpu_probe_mips()
1368 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1372 c->cputype = CPU_M14KC; in cpu_probe_mips()
1373 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1377 c->cputype = CPU_M14KEC; in cpu_probe_mips()
1378 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1382 c->cputype = CPU_1004K; in cpu_probe_mips()
1383 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1388 c->cputype = CPU_1074K; in cpu_probe_mips()
1389 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1393 c->cputype = CPU_INTERAPTIV; in cpu_probe_mips()
1398 c->cputype = CPU_INTERAPTIV; in cpu_probe_mips()
1403 c->cputype = CPU_PROAPTIV; in cpu_probe_mips()
1407 c->cputype = CPU_PROAPTIV; in cpu_probe_mips()
1411 c->cputype = CPU_P5600; in cpu_probe_mips()
1415 c->cputype = CPU_P6600; in cpu_probe_mips()
1419 c->cputype = CPU_I6400; in cpu_probe_mips()
1423 c->cputype = CPU_I6500; in cpu_probe_mips()
1427 c->cputype = CPU_M5150; in cpu_probe_mips()
1431 c->cputype = CPU_M6250; in cpu_probe_mips()
1442 switch (__get_cpu_type(c->cputype)) { in cpu_probe_mips()
1448 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; in cpu_probe_mips()
1451 c->options |= MIPS_CPU_SHARED_FTLB_RAM; in cpu_probe_mips()
1457 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for in cpu_probe_mips()
1460 switch (__get_cpu_type(c->cputype)) { in cpu_probe_mips()
1466 c->options |= MIPS_CPU_FTLBPAREX; in cpu_probe_mips()
1474 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_alchemy()
1477 c->cputype = CPU_ALCHEMY; in cpu_probe_alchemy()
1478 switch ((c->processor_id >> 24) & 0xff) { in cpu_probe_alchemy()
1485 case 2: in cpu_probe_alchemy()
1493 if ((c->processor_id & PRID_REV_MASK) == 2) in cpu_probe_alchemy()
1505 c->cputype = CPU_ALCHEMY; in cpu_probe_alchemy()
1515 c->writecombine = _CACHE_UNCACHED_ACCELERATED; in cpu_probe_sibyte()
1516 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_sibyte()
1518 c->cputype = CPU_SB1; in cpu_probe_sibyte()
1521 if ((c->processor_id & PRID_REV_MASK) < 0x02) in cpu_probe_sibyte()
1522 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); in cpu_probe_sibyte()
1525 c->cputype = CPU_SB1A; in cpu_probe_sibyte()
1534 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_sandcraft()
1536 c->cputype = CPU_SR71000; in cpu_probe_sandcraft()
1538 c->scache.ways = 8; in cpu_probe_sandcraft()
1539 c->tlbsize = 64; in cpu_probe_sandcraft()
1547 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_nxp()
1549 c->cputype = CPU_PR4450; in cpu_probe_nxp()
1559 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_broadcom()
1562 c->cputype = CPU_BMIPS32; in cpu_probe_broadcom()
1569 c->cputype = CPU_BMIPS3300; in cpu_probe_broadcom()
1575 int rev = c->processor_id & PRID_REV_MASK; in cpu_probe_broadcom()
1579 c->cputype = CPU_BMIPS4380; in cpu_probe_broadcom()
1582 c->options |= MIPS_CPU_RIXI; in cpu_probe_broadcom()
1585 c->cputype = CPU_BMIPS4350; in cpu_probe_broadcom()
1593 c->cputype = CPU_BMIPS5000; in cpu_probe_broadcom()
1594 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) in cpu_probe_broadcom()
1599 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; in cpu_probe_broadcom()
1609 c->options &= ~MIPS_CPU_4K_CACHE; in cpu_probe_cavium()
1610 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_cavium()
1614 c->cputype = CPU_CAVIUM_OCTEON; in cpu_probe_cavium()
1621 c->cputype = CPU_CAVIUM_OCTEON_PLUS; in cpu_probe_cavium()
1631 c->cputype = CPU_CAVIUM_OCTEON2; in cpu_probe_cavium()
1639 c->cputype = CPU_CAVIUM_OCTEON3; in cpu_probe_cavium()
1645 c->cputype = CPU_UNKNOWN; in cpu_probe_cavium()
1660 c->ases |= MIPS_ASE_LOONGSON_MMI; in decode_cpucfg()
1663 c->ases |= MIPS_ASE_LOONGSON_EXT; in decode_cpucfg()
1666 c->ases |= MIPS_ASE_LOONGSON_EXT2; in decode_cpucfg()
1669 c->options |= MIPS_CPU_LDPTE; in decode_cpucfg()
1670 c->guest.options |= MIPS_CPU_LDPTE; in decode_cpucfg()
1674 c->ases |= MIPS_ASE_LOONGSON_CAM; in decode_cpucfg()
1679 c->cputype = CPU_LOONGSON64; in cpu_probe_loongson()
1681 /* All Loongson processors covered here define ExcCode 16 as GSExc. */ in cpu_probe_loongson()
1683 c->options |= MIPS_CPU_GSEXCEX; in cpu_probe_loongson()
1685 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_loongson()
1686 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ in cpu_probe_loongson()
1687 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_loongson()
1692 __cpu_name[cpu] = "Loongson-2K"; in cpu_probe_loongson()
1697 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | in cpu_probe_loongson()
1700 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ in cpu_probe_loongson()
1701 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_loongson()
1704 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_loongson()
1710 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_loongson()
1716 * Loongson-3 Classic did not implement MIPS standard TLBINV in cpu_probe_loongson()
1720 * Also some early Loongson-3A2000 had wrong TLB type in Config in cpu_probe_loongson()
1723 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; in cpu_probe_loongson()
1724 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | in cpu_probe_loongson()
1726 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ in cpu_probe_loongson()
1731 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_loongson()
1739 panic("Unknown Loongson Processor ID!"); in cpu_probe_loongson()
1758 c->options &= ~MIPS_CPU_COUNTER; in cpu_probe_ingenic()
1762 c->icache.flags |= MIPS_CACHE_VTAG; in cpu_probe_ingenic()
1764 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_ingenic()
1777 switch (c->processor_id & PRID_COMP_MASK) { in cpu_probe_ingenic()
1785 c->isa_level &= ~MIPS_CPU_ISA_M32R2; in cpu_probe_ingenic()
1788 if (c->processor_id == 0x2ed0024f) in cpu_probe_ingenic()
1789 c->options |= MIPS_CPU_FPU; in cpu_probe_ingenic()
1798 * (line 21 in the tlb-funcs.S) when starting the init process. in cpu_probe_ingenic()
1814 /* Ingenic uses the WA bit to achieve write-combine memory writes */ in cpu_probe_ingenic()
1815 c->writecombine = _CACHE_CACHABLE_WA; in cpu_probe_ingenic()
1816 c->cputype = CPU_XBURST; in cpu_probe_ingenic()
1820 /* XBurst®2 with MXU2.1 SIMD ISA */ in cpu_probe_ingenic()
1822 c->cputype = CPU_XBURST; in cpu_probe_ingenic()
1853 c->processor_id = PRID_IMP_UNKNOWN; in cpu_probe()
1854 c->fpu_id = FPIR_IMP_NONE; in cpu_probe()
1855 c->cputype = CPU_UNKNOWN; in cpu_probe()
1856 c->writecombine = _CACHE_UNCACHED; in cpu_probe()
1858 c->fpu_csr31 = FPU_CSR_RN; in cpu_probe()
1859 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; in cpu_probe()
1861 c->processor_id = read_c0_prid(); in cpu_probe()
1862 switch (c->processor_id & PRID_COMP_MASK) { in cpu_probe()
1900 BUG_ON(c->cputype == CPU_UNKNOWN); in cpu_probe()
1907 BUG_ON(current_cpu_type() != c->cputype); in cpu_probe()
1915 c->options |= MIPS_CPU_RIXIEX; in cpu_probe()
1919 c->options &= ~MIPS_CPU_FPU; in cpu_probe()
1922 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); in cpu_probe()
1925 c->options &= ~MIPS_CPU_HTW; in cpu_probe()
1930 if (c->options & MIPS_CPU_FPU) in cpu_probe()
1936 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; in cpu_probe()
1938 c->options |= MIPS_CPU_PCI; in cpu_probe()
1941 c->srsets = 1; in cpu_probe()
1947 c->msa_id = cpu_get_msa_id(); in cpu_probe()
1948 WARN(c->msa_id & MSA_IR_WRPF, in cpu_probe()
1991 /* Synthesize CPUCFG data if running on Loongson processors; in cpu_probe()
1992 * no-op otherwise. in cpu_probe()
2000 __ua_limit = ~((1ull << cpu_vmbits) - 1); in cpu_probe()
2011 smp_processor_id(), c->processor_id, cpu_name_string()); in cpu_report()
2012 if (c->options & MIPS_CPU_FPU) in cpu_report()
2013 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); in cpu_report()
2015 pr_info("MSA revision is: %08x\n", c->msa_id); in cpu_report()
2024 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; in cpu_set_cluster()
2025 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; in cpu_set_cluster()
2033 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; in cpu_set_core()
2034 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; in cpu_set_core()
2046 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; in cpu_set_vpe_id()
2047 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; in cpu_set_vpe_id()