Lines Matching refs:t0
103 li t0, 0xff
104 sw t0, GCR_CL_COHERENCE_OFS(s1)
109 1: mfc0 t0, CP0_CONFIG
110 ori t0, 0x7
111 xori t0, 0x7
112 or t0, t0, s0
113 mtc0 t0, CP0_CONFIG
117 PTR_LA t0, 1f
118 jr t0
196 has_mt t0, 3f
212 1: mfc0 t0, CP0_MVPCONTROL
213 ori t0, t0, MVPCONTROL_VPC
214 mtc0 t0, CP0_MVPCONTROL
217 mfc0 t0, CP0_MVPCONF0
218 srl t0, t0, MVPCONF0_PVPE_SHIFT
219 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
220 addiu ta3, t0, 1
223 beqz t0, 2f
237 li t0, VPECONF0_MVP
239 or t0, t0, t1
240 mttc0 t0, CP0_VPECONF0
246 li t0, TCHALT_H
247 mttc0 t0, CP0_TCHALT
251 slt t0, ta1, ta3
252 bnez t0, 1b
256 2: mfc0 t0, CP0_MVPCONTROL
257 xori t0, t0, MVPCONTROL_VPC
258 mtc0 t0, CP0_MVPCONTROL
274 lw t0, GCR_CL_ID_OFS(s1)
276 mul t0, t0, t1
279 PTR_ADDU v0, t0, t1
331 has_vp t0, 5f
353 has_mt t0, 5f
375 1: andi t0, ta2, 1
376 beqz t0, 2f
380 mfc0 t0, CP0_VPECONTROL
381 ori t0, t0, VPECONTROL_TARGTC
382 xori t0, t0, VPECONTROL_TARGTC
383 or t0, t0, ta1
384 mtc0 t0, CP0_VPECONTROL
392 mftc0 t0, CP0_TCHALT
393 beqz t0, 2f
397 li t0, VPEBOOTCFG_SIZE
398 mul t0, t0, ta1
399 PTR_ADDU t0, t0, ta3
402 lw t1, VPEBOOTCFG_PC(t0)
406 lw t1, VPEBOOTCFG_SP(t0)
410 lw t1, VPEBOOTCFG_GP(t0)
414 mfc0 t0, CP0_CONFIG
415 mttc0 t0, CP0_CONFIG
421 mfc0 t0, CP0_CONFIG, 3
422 and t0, t0, MIPS_CONF3_SC
423 beqz t0, 3f
425 mfc0 t0, CP0_SEGCTL0
426 mttc0 t0, CP0_SEGCTL0
427 mfc0 t0, CP0_SEGCTL1
428 mttc0 t0, CP0_SEGCTL1
429 mfc0 t0, CP0_SEGCTL2
430 mttc0 t0, CP0_SEGCTL2
437 mftc0 t0, CP0_TCSTATUS
439 and t0, t0, t1
440 ori t0, t0, TCSTATUS_A
441 mttc0 t0, CP0_TCSTATUS
447 mftc0 t0, CP0_VPECONF0
448 ori t0, t0, VPECONF0_VPA
449 mttc0 t0, CP0_VPECONF0
467 li t0, 1
468 sll t0, t0, a1
469 and t0, t0, t8
470 bnez t0, 2f
474 li t0, TCHALT_H
475 mtc0 t0, CP0_TCHALT
476 PTR_LA t0, 1f
477 1: jr.hb t0
507 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
508 beqz t0, icache_done
510 sllv t0, t1, t0
522 mul t1, t1, t0
528 PTR_ADD a0, a0, t0
534 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
535 beqz t0, dcache_done
537 sllv t0, t1, t0
549 mul t1, t1, t0
554 PTR_SUBU a1, a1, t0
557 PTR_ADD a0, a0, t0