Lines Matching +full:li +full:-
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include <asm/asm-offsets.h>
17 #include <asm/smp-cps.h>
51 * Set dest to non-zero if the core supports the MT ASE, else zero. If
66 * Set dest to non-zero if the core supports MIPSr6 multithreading
103 li t0, 0xff
131 /* Skip core-level init if we started up coherent */
135 /* Perform any further required core-level initialisation */
227 li ta1, 1
236 /* Set exclusive TC, non-active, master */
237 li t0, VPECONF0_MVP
242 /* Set TC non-active, non-allocatable */
246 li t0, TCHALT_H
267 * mips_cps_get_bootcfg() - retrieve boot configuration pointers
275 li t1, COREBOOTCFG_SIZE
282 li t9, 0
287 * Assume non-contiguous numbering. Perhaps some day we'll need
304 li t2, 31
306 li t2, 1
308 addiu t1, t1, -1
316 li t1, VPEBOOTCFG_SIZE
372 li ta1, 0
397 li t0, VPEBOOTCFG_SIZE
419 * CONFIG3 must exist to be running MT startup - just read it.
438 li t1, ~TCSTATUS_IXMT
467 li t0, 1
474 li t0, TCHALT_H
506 /* Detect I-cache line size */
509 li t1, 2
512 /* Detect I-cache size */
516 li t3, 32
519 1: /* At this point t1 == I-cache sets per way */
525 li a0, CKSEG0
533 /* Detect D-cache line size */
536 li t1, 2
539 /* Detect D-cache size */
543 li t3, 32
546 1: /* At this point t1 == D-cache sets per way */
552 li a0, CKSEG0