Lines Matching +full:li +full:-
7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
112 * Description: compute the I-cache size and I-cache line size
131 * vi) 0x5 - 0x7: Reserved.
139 li v0, 0x40
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
161 li v1, 1
174 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 * 4-way, v) 0x4 - 0x7: Reserved.
207 * Description: compute the D-cache size and D-cache line size.
224 * vi) 0x5 - 0x7: Reserved.
232 li v0, 0x40
239 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
253 li v1, 1
265 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
266 * 4-way, v) 0x4 - 0x7: Reserved.
300 * Description: Enable I and D caches, initialize I and D-caches, also set
301 * hardware delay for d-cache (TP0).
323 * Description: Enable I and D caches, and initialize I and D-caches
351 jal size_i_cache /* v0 = i-cache size, v1 = i-cache line size */
375 li a0, KSEG0
379 * Now we can run from I-$, kseg 0
392 jal size_d_cache /* v0 = d-cache size, v1 = d-cache line size */
396 li a0, KSEG0
419 /* enable Bus error for I-fetch */
421 li t1, 0x4
427 li t1, 0x4
433 li t1, 0x4
456 li t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
460 li t1, BRCM_BrPRED_BHT_ENABLE
465 li t1, 8
487 li t1, ~(CP0_BRCM_MODE_Luc_MASK)
510 li t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
533 li t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
535 li t1, CP0_BRCM_MODE_SET_MASK
555 li t0, 0x5a455048
559 li t1, 0x09008000 /* turn off pref, jtb */
565 li t0, 0x0
589 li t2, 0x90000000 | BRCM_ZSC_ALL_REGS_SELECT | BRCM_ZSC_CONFIG_REG
594 li t1, ~(BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
601 li t1, (BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
636 li a0, 1
656 li a0, 0
692 li t1, ~JTB_CS_CNTL_MASK
694 li t2, RESET_CALL_RETURN_STACK_THIS_THREAD
701 li t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
715 * Description: Enable I and D caches, and initialize I and D-caches