mips/kernel/bmips_5xxx_init.S

7  * Copyright (C) 2011-2012 by Broadcom Corporation
34 	addiu		t1, t1, -1	;	\
64 #define CP0_DCACHE_TAG_LO	$28, 2
68 #define CP0_DCACHE_TAG_HI	$29, 2
84 #define BRCM_ZSC_REQ_BUFFER_REG			2 << 3
107 .align 2
112  * Description: compute the I-cache size and I-cache line size
126 	 * Determine sets per way: IS
128 	 * This field contains the number of sets (i.e., indices) per way of
131 	 * vi) 0x5 - 0x7: Reserved.
137 	/* sets per way = (64<<IS) */
146 	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
158 	/* line size = 2 ^ (IL+1) */
164 	/* v0 now have sets per way, multiply it by line size now
174 	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 	 * 4-way, v) 0x4 - 0x7: Reserved.
207  * Description: compute the D-cache size and D-cache line size.
219 	 * Determine sets per way: IS
221 	 * This field contains the number of sets (i.e., indices) per way of
224 	 * vi) 0x5 - 0x7: Reserved.
230 	/* sets per way = (64<<IS) */
239 	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
250 	/* line size = 2 ^ (IL+1) */
256 	/* v0 now have sets per way, multiply it by line size now
265 	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
266 	 * 4-way, v) 0x4 - 0x7: Reserved.
300  * Description: Enable I and D caches, initialize I and D-caches, also set
301  *		hardware delay for d-cache (TP0).
323  * Description: Enable I and D caches, and initialize I and D-caches
351 	jal	size_i_cache	/* v0 = i-cache size, v1 = i-cache line size */
379 	 * Now we can run from I-$, kseg 0
392 	jal	size_d_cache	/* v0 = d-cache size, v1 = d-cache line size */
419 	/* enable Bus error for I-fetch */
432 	mfc0	t0, CP0_CACHEERR, 2
435 	mtc0	t0, CP0_CACHEERR, 2
688 	mfc0	t0, $22, 2
696 	mtc0	t0, $22, 2
703 	mtc0	t0, $22, 2
715  * Description: Enable I and D caches, and initialize I and D-caches