Lines Matching +full:0 +full:x0000fc00
18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
28 #define WIDGET_TFLUSH 0x54
31 #define WIDGET_REV_NUM 0xf0000000
32 #define WIDGET_PART_NUM 0x0ffff000
33 #define WIDGET_MFG_NUM 0x00000ffe
43 #define WIDGET_LLP_REC_CNT 0xff000000
44 #define WIDGET_LLP_TX_CNT 0x00ff0000
45 #define WIDGET_PENDING 0x0000001f
48 #define WIDGET_ERR_UPPER_ADDR_ONLY 0x0000ffff
51 #define WIDGET_F_BAD_PKT 0x00010000
52 #define WIDGET_LLP_XBAR_CRD 0x0000f000
54 #define WIDGET_CLR_RLLP_CNT 0x00000800
55 #define WIDGET_CLR_TLLP_CNT 0x00000400
56 #define WIDGET_SYS_END 0x00000200
57 #define WIDGET_MAX_TRANS 0x000001f0
58 #define WIDGET_WIDGET_ID 0x0000000f
61 #define WIDGET_INT_VECTOR 0xff000000
63 #define WIDGET_TARGET_ID 0x000f0000
65 #define WIDGET_UPP_ADDR 0x0000ffff
68 #define WIDGET_DIDN 0xf0000000
69 #define WIDGET_SIDN 0x0f000000
70 #define WIDGET_PACTYP 0x00f00000
71 #define WIDGET_TNUM 0x000f8000
72 #define WIDGET_COHERENT 0x00004000
73 #define WIDGET_DS 0x00003000
74 #define WIDGET_GBR 0x00000800
75 #define WIDGET_VBPM 0x00000400
76 #define WIDGET_ERROR 0x00000200
77 #define WIDGET_BARRIER 0x00000100
80 #define WIDGET_LLP_MAXRETRY 0x03ff0000
82 #define WIDGET_LLP_NULLTIMEOUT 0x0000fc00
84 #define WIDGET_LLP_MAXBURST 0x000003ff
85 #define WIDGET_LLP_MAXBURST_SHFT 0
88 #define WIDGET_XBOW_MFGR_NUM 0x0 /* IP30 XBow Chip */
89 #define WIDGET_XXBOW_MFGR_NUM 0x0 /* IP35 Xbow + XBridge Chip */
90 #define WIDGET_ODYS_MFGR_NUM 0x023 /* Odyssey / VPro GFX */
91 #define WIDGET_TPU_MFGR_NUM 0x024 /* Tensor Processor Unit */
92 #define WIDGET_XBRDG_MFGR_NUM 0x024 /* IP35 XBridge Chip */
93 #define WIDGET_HEART_MFGR_NUM 0x036 /* IP30 HEART Chip */
94 #define WIDGET_BRIDG_MFGR_NUM 0x036 /* PCI Bridge */
95 #define WIDGET_HUB_MFGR_NUM 0x036 /* IP27 Hub Chip */
96 #define WIDGET_BDRCK_MFGR_NUM 0x036 /* IP35 Bedrock Chip */
97 #define WIDGET_IMPCT_MFGR_NUM 0x2aa /* HQ4 / Impact GFX */
98 #define WIDGET_KONA_MFGR_NUM 0x2aa /* InfiniteReality3 / Kona GFX */
102 #define WIDGET_XBOW_PART_NUM 0x0000
103 #define WIDGET_HEART_PART_NUM 0xc001
104 #define WIDGET_BRIDG_PART_NUM 0xc002
105 #define WIDGET_IMPCT_PART_NUM 0xc003
106 #define WIDGET_ODYS_PART_NUM 0xc013
107 #define WIDGET_HUB_PART_NUM 0xc101
108 #define WIDGET_KONA_PART_NUM 0xc102
109 #define WIDGET_BDRCK_PART_NUM 0xc110
110 #define WIDGET_TPU_PART_NUM 0xc202
111 #define WIDGET_XXBOW_PART_NUM 0xd000
112 #define WIDGET_XBRDG_PART_NUM 0xd002
177 {"0", NULL},
211 widgetreg_t w_pad_0; /* 0x00 */
212 widgetreg_t w_id; /* 0x04 */
213 widgetreg_t w_pad_1; /* 0x08 */
214 widgetreg_t w_status; /* 0x0c */
215 widgetreg_t w_pad_2; /* 0x10 */
216 widgetreg_t w_err_upper_addr; /* 0x14 */
217 widgetreg_t w_pad_3; /* 0x18 */
218 widgetreg_t w_err_lower_addr; /* 0x1c */
219 widgetreg_t w_pad_4; /* 0x20 */
220 widgetreg_t w_control; /* 0x24 */
221 widgetreg_t w_pad_5; /* 0x28 */
222 widgetreg_t w_req_timeout; /* 0x2c */
223 widgetreg_t w_pad_6; /* 0x30 */
224 widgetreg_t w_intdest_upper_addr; /* 0x34 */
225 widgetreg_t w_pad_7; /* 0x38 */
226 widgetreg_t w_intdest_lower_addr; /* 0x3c */
227 widgetreg_t w_pad_8; /* 0x40 */
228 widgetreg_t w_err_cmd_word; /* 0x44 */
229 widgetreg_t w_pad_9; /* 0x48 */
230 widgetreg_t w_llp_cfg; /* 0x4c */
231 widgetreg_t w_pad_10; /* 0x50 */
232 widgetreg_t w_tflush; /* 0x54 */