sn/sn0/hubpi.h

8  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
28 #define PI_CPU_PROTECT		0x000000 /* CPU Protection		    */
29 #define PI_PROT_OVERRD		0x000008 /* Clear CPU Protection bit	    */
32 #define PI_CPU_NUM		0x000020 /* CPU Number ID		    */
57 #define PI_CPU_PRESENT_A	0x000040 /* CPU Present A		    */
58 #define PI_CPU_PRESENT_B	0x000048 /* CPU Present B		    */
59 #define PI_CPU_ENABLE_A		0x000050 /* CPU Enable A		    */
60 #define PI_CPU_ENABLE_B		0x000058 /* CPU Enable B		    */
63 #define PI_NMI_A		0x000070 /* NMI to CPU A		    */
64 #define PI_NMI_B		0x000078 /* NMI to CPU B		    */
65 #define PI_NMI_OFFSET		(PI_NMI_B - PI_NMI_A)
71 #define PI_INT_PEND0		0x000098 /* Read to get pending ints	    */
72 #define PI_INT_PEND1		0x0000a0 /* Read to get pending ints	    */
73 #define PI_INT_MASK0_A		0x0000a8 /* Interrupt Mask 0 for CPU A	    */
74 #define PI_INT_MASK1_A		0x0000b0 /* Interrupt Mask 1 for CPU A	    */
75 #define PI_INT_MASK0_B		0x0000b8 /* Interrupt Mask 0 for CPU B	    */
76 #define PI_INT_MASK1_B		0x0000c0 /* Interrupt Mask 1 for CPU B	    */
82 #define PI_CC_PEND_SET_A	0x0000c8 /* CC Interrupt Pending Set, CPU A */
83 #define PI_CC_PEND_SET_B	0x0000d0 /* CC Interrupt Pending Set, CPU B */
84 #define PI_CC_PEND_CLR_A	0x0000d8 /* CC Interrupt Pending Clr, CPU A */
85 #define PI_CC_PEND_CLR_B	0x0000e0 /* CC Interrupt Pending Clr, CPU B */
100 #define PI_RT_EN_A		0x000140 /* RT int for CPU A enable	    */
101 #define PI_RT_EN_B		0x000148 /* RT int for CPU B enable	    */
102 #define PI_PROF_EN_A		0x000150 /* PROF int for CPU A enable	    */
103 #define PI_PROF_EN_B		0x000158 /* PROF int for CPU B enable	    */
109 /* Built-In Self Test support */
112 #define PI_BIST_READ_DATA	0x000208 /* BIST read data		    */
132 #define PI_GFX_OFFSET		(PI_GFX_PAGE_B - PI_GFX_PAGE_A)
137 #define PI_ERR_INT_MASK_A	0x000408 /* Error Interrupt mask for CPU A  */
138 #define PI_ERR_INT_MASK_B	0x000410 /* Error Interrupt mask for CPU B  */
139 #define PI_ERR_STACK_ADDR_A	0x000418 /* Error stack address for CPU A   */
140 #define PI_ERR_STACK_ADDR_B	0x000420 /* Error stack address for CPU B   */
143 #define PI_ERR_STATUS0_A_RCLR	0x000438 /* Error Status 0A clear on read   */
145 #define PI_ERR_STATUS1_A_RCLR	0x000448 /* Error Status 1A clear on read   */
147 #define PI_ERR_STATUS0_B_RCLR	0x000458 /* Error Status 0B clear on read   */
149 #define PI_ERR_STATUS1_B_RCLR	0x000468 /* Error Status 1B clear on read   */
150 #define PI_SPOOL_CMP_A		0x000470 /* Spool compare for CPU A	    */
151 #define PI_SPOOL_CMP_B		0x000478 /* Spool compare for CPU B	    */
158 #define PI_NACK_CNT_B		0x0004b0 /*	"	" for CPU B	    */
160 #define PI_STACKADDR_OFFSET	(PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
161 #define PI_ERRSTAT_OFFSET	(PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
162 #define PI_RDCLR_OFFSET		(PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
231  * Use the write types if WRBRRB is 1 else use the read types
284 /* Error type in the error status or stack on Read CRBs */
294 /* Read or Write CRB in error status or stack */
307        ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)