Lines Matching +full:0 +full:x600000
24 #define NI_BASE 0x600000
25 #define NI_BASE_TABLES 0x630000
27 #define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */
28 #define NI_PORT_RESET 0x600008 /* Reset the network interface */
29 #define NI_PROTECTION 0x600010 /* NI register access permissions */
30 #define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */
31 #define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */
32 #define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */
33 #define NI_DIAG_PARMS 0x600110 /* Parameters for diags */
35 #define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
36 #define NI_VECTOR 0x600208 /* Vector PIO route */
37 #define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
38 #define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
39 #define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
40 #define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
41 #define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
43 #define NI_IO_PROTECT 0x600400 /* PIO protection bits */
44 #define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
46 #define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */
47 #define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
48 #define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */
49 #define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */
50 #define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */
51 #define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */
52 #define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */
53 #define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */
57 #define NI_PORT_PARMS 0x608000 /* LLP Parameters */
58 #define NI_PORT_ERROR 0x608008 /* LLP Errors */
59 #define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */
61 #define NI_META_TABLE0 0x638000 /* First meta routing table entry */
65 #define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */
75 #define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
77 #define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
78 #define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */
79 #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
82 #define MORE_MEMORY 0
87 #define REGIONSIZE_COARSE 0
89 #define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
91 #define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
92 #define NSRI_CHIPID_SHFT 0
93 #define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
99 #define NASID_TO_FINEREG_SHFT 0
115 #define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
117 #define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
120 #define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
122 #define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
137 #define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
139 #define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
140 #define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
141 #define NVP_TYPE_SHFT 0
142 #define NVP_TYPE_MASK (UINT64_CAST 0x3)
149 #define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
151 #define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
153 #define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
154 #define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
155 #define NVS_TYPE_SHFT 0
156 #define NVS_TYPE_MASK (UINT64_CAST 0x7)
157 #define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
160 #define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */
175 #define NAGE_AGE_SHFT 0
176 #define NAGE_AGE_MASK (UINT64_CAST 0xff)
179 #define VCHANNEL_A 0
186 #define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
187 #define NPP_MAXBURST_SHFT 0
188 #define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
190 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
192 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
203 #define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
205 #define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
207 #define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
209 #define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
210 #define NPE_SNERRCOUNT_SHFT 0
211 #define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
212 #define NPE_MASK 0x3effffffff
214 #define NPE_COUNT_MAX 0xff
223 #define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
227 #define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
249 #define NI_LLP_RETRY_MAX 0xff
250 #define NI_LLP_CB_MAX 0xff
251 #define NI_LLP_SN_MAX 0xff