asm/sn/ioc3.h

1 /* SPDX-License-Identifier: GPL-2.0 */
50 	u8	fill0[0x151 - 0x142 - 1];
56 	u8	fill1[0x159 - 0x153 - 1];
62 	u8	fill2[0x16a - 0x15b - 1];
67 	u8	fill3[0x170 - 0x16b - 1];
153 	u32	pad1[(0x20000 - 0x00154) / 4];
157 	u32	pad2[(0x40000 - 0x20180) / 4];
160 	u32	ssram[(0x80000 - 0x40000) / 4];
163 	   0x80000 -   Access to the generic devices selected with   DEV0
165 	   0xA0000 -   Access to the generic devices selected with   DEV1
167 	   0xC0000 -   Access to the generic devices selected with   DEV2
169 	   0xE0000 -   Access to the generic devices selected with   DEV3
242 /* ------------------------------------------------------------------------- */
347 #define SSCR_RX_RING_DCD 0x00040000	/* post RX record on delta-DCD */
348 #define SSCR_RX_RING_CTS 0x00080000	/* post RX record on delta-CTS */
349 #define SSCR_HIGH_SPD	0x00100000	/* 4X speed */
382 #define SHADOW_DCTS	0x00010000	/* delta clear to send */
383 #define SHADOW_DDCD	0x00080000	/* delta data carrier detect */
403 #define SIO_IR_SA_DELTA_DCD	0x00000010	/* port A delta DCD */
404 #define SIO_IR_SA_DELTA_CTS	0x00000020	/* port A delta CTS */
405 #define SIO_IR_SA_INT		0x00000040	/* port A pass-thru intr */
417 #define SIO_IR_PP_INT		0x00040000	/* P port pass-thru intr */
455 #define SIO_CR_ARB_DIAG_IDLE	0x00400000	/* 0 -> active request (ro) */
471 #define INT_OUT_US_TO_COUNT(x)		/* convert uS to a count value */ \  argument
472 	(((x) * 10 + INT_OUT_NS_PER_TICK / 200) *	\
473 	 100 / INT_OUT_NS_PER_TICK - 1)
474 #define INT_OUT_COUNT_TO_US(x)		/* convert count value to uS */ \  argument
475 	(((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
481 #define GPCR_DIR_PIN(x) (1<<(x))	/* access one of the DIR bits */  argument
483 #define GPCR_EDGE_PIN(x) (1<<((x)+15))	/* access one of the EDGE bits */  argument
537 #define ERCSR_THRESH_MASK	0x000001ff	/* enet RX threshold */
593 /* subsystem IDs supplied by card detection in pci-xtalk-bridge */