Lines Matching refs:_SB_MAKEMASK1
211 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
212 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
213 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
214 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
221 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
222 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
223 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
224 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
225 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
236 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
237 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
238 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
239 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
240 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
241 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
242 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
251 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
252 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
259 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
270 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
271 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
272 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
273 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
274 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
278 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
279 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
281 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
282 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
284 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
285 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
286 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
288 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
289 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
292 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
326 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
342 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
363 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
364 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
392 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
393 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
416 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
468 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
469 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
470 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
471 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
472 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
507 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
508 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
509 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
510 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
511 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
512 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
513 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
514 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
516 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
544 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
545 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
546 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
547 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
548 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
549 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
550 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
633 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
634 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
635 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
636 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
637 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
638 #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
639 #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)