Lines Matching +full:x +full:-
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 * Memory Channel Config Register (table 6-14)
34 #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) argument
35 #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) argument
39 #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) argument
40 #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) argument
47 #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) argument
48 #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) argument
55 #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) argument
56 #define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) argument
63 #define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) argument
64 #define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) argument
73 #define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) argument
74 #define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) argument
79 #define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) argument
80 #define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) argument
85 #define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) argument
86 #define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) argument
95 #define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) argument
96 #define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) argument
122 * Memory clock config register (Table 6-15)
129 #define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) argument
130 #define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) argument
149 #define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) argument
150 #define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) argument
163 #define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) argument
164 #define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) argument
169 #define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) argument
170 #define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) argument
175 #define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) argument
176 #define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) argument
179 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
181 #endif /* 1250 PASS3 || 112x PASS1 */
187 #define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) argument
188 #define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) argument
193 #define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) argument
194 #define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) argument
199 #define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) argument
200 #define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) argument
205 #define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) argument
206 #define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) argument
221 * DRAM Command Register (Table 6-13)
226 #define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) argument
227 #define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) argument
253 * DRAM Mode Register (Table 6-14)
258 #define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) argument
259 #define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) argument
264 #define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) argument
265 #define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) argument
270 #define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) argument
271 #define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) argument
283 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
286 #endif /* 1250 PASS3 || 112x PASS1 */
291 * SDRAM Timing Register (Table 6-15)
300 #define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) argument
301 #define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) argument
307 #define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) argument
308 #define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) argument
318 #define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) argument
319 #define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) argument
325 #define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) argument
326 #define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) argument
332 #define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) argument
333 #define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) argument
339 #define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) argument
340 #define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) argument
346 #define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) argument
347 #define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) argument
353 #define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) argument
354 #define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) argument
363 #define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) argument
364 #define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) argument
370 #define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) argument
371 #define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) argument
395 * Chip Select Start Address Register (Table 6-17)
400 #define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) argument
401 #define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) argument
405 #define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) argument
406 #define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) argument
410 #define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) argument
411 #define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) argument
415 #define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) argument
416 #define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) argument
419 * Chip Select End Address Register (Table 6-18)
424 #define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) argument
425 #define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) argument
429 #define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) argument
430 #define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) argument
434 #define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) argument
435 #define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) argument
439 #define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) argument
440 #define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) argument
443 * Chip Select Interleave Register (Table 6-19)
451 #define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) argument
457 * Row Address Bits Register (Table 6-20)
465 #define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) argument
472 * Column Address Bits Register (Table 6-21)
480 #define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) argument
487 * Bank Address Bits Register (Table 6-22)
495 #define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) argument
501 * Chip Select Attribute Register (Table 6-23)
511 #define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) argument
512 #define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) argument
516 #define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) argument
517 #define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) argument
521 #define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) argument
522 #define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) argument
526 #define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) argument
527 #define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) argument
530 * ECC Test ECC Register (Table 6-25)