Lines Matching refs:_SB_MAKE64
46 #define S_DMA_DESC_TYPE _SB_MAKE64(1)
65 #define S_DMA_INT_PKTCNT _SB_MAKE64(8)
70 #define S_DMA_RINGSZ _SB_MAKE64(16)
75 #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
80 #define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
108 #define S_DMA_HDR_SIZE _SB_MAKE64(21)
115 #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
120 #define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
149 #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
151 #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
162 #define S_DMA_OODLOST_RX _SB_MAKE64(0)
166 #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
179 #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
185 #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
191 #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
195 #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
201 #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
209 #define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
219 #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
225 #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
231 #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
234 #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
237 #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
245 #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
251 #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
259 #define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
318 #define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
319 #define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
320 #define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
321 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
322 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
323 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
324 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
325 #define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
326 #define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
327 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
328 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
329 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
330 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
331 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
332 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
333 #define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
378 #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
381 #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
386 #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
418 #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
421 #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
436 #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
442 #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
458 #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
464 #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
478 #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
484 #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
490 #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
508 #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
518 #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
531 #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
572 #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
575 #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)