Lines Matching full:gio

21 #define SGIMC_CCTRL0_EPERRGIO	0x00000020 /* GIO parity error enable */
37 #define SGIMC_CCTRL0_GIOBTOB	0x08000000 /* Allow GIO back to back writes */
40 #define SGIMC_CCTRL1_EGIOTIMEO	0x00000010 /* GIO bus timeout enable */
75 #define SGIMC_GIOPAR_HPC64	0x00000001 /* HPC talks to GIO using 64-bits */
76 #define SGIMC_GIOPAR_GFX64	0x00000002 /* GFX talks to GIO using 64-bits */
79 #define SGIMC_GIOPAR_EISA64	0x00000010 /* EISA bus talks 64-bits to GIO */
80 #define SGIMC_GIOPAR_HPC264	0x00000020 /* 2nd HPX talks 64-bits to GIO */
112 	volatile u32 gmacc;	   /* Mem access config for GIO */
117 	/* Error address/status regs from GIO and CPU perspectives. */
132 	volatile u32 gerr;	/* Error address reg for GIO */
134 	volatile u32 gstat;	/* Status reg for GIO */
137 #define SGIMC_GSTAT_TIME	0x00000400 /* GIO bus timed out */
148 	volatile u32 mlock;		/* Global GIO memory access lock */
150 	volatile u32 elock;		/* Locks EISA from GIO accesses */
152 	/* GIO dma control registers. */
154 	volatile u32 gio_dma_trans;	/* DMA mask to translation GIO addrs */
156 	volatile u32 gio_dma_sbits;	/* DMA GIO addr substitution bits */
202 	volatile u32 gmaddronly;	/* Set GIO DMA but don't start trans */
204 	volatile u32 dmaddnpgo;		/* Set GIO DMA addr + start transfer */