asm/sgi/hpc3.h

36 /* The set of regs for each HPC3 PBUS DMA channel. */
38 	volatile u32 pbdma_bptr;	/* pbus dma channel buffer ptr */
39 	volatile u32 pbdma_dptr;	/* pbus dma channel desc ptr */
40 	u32 _unused0[0x1000/4 - 2];	/* padding */
41 	volatile u32 pbdma_ctrl;	/* pbus dma channel control register has
46 #define HPC3_PDMACTRL_ISACT	0x00000002 /* channel active */
54 #define HPC3_PDMACTRL_HW	0x0000ff00 /* DMA High-water mark */
58 	u32 _unused1[0x1000/4 - 1];	/* padding */
63 	volatile u32 cbptr;	/* current dma buffer ptr, diagnostic use only */
65 	u32 _unused0[0x1000/4 - 2];	/* padding */
76 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
81 	volatile u32 gfptr;	/* current GIO fifo ptr */
82 	volatile u32 dfptr;	/* current device fifo ptr */
89 #define HPC3_SDCFG_HW	0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW	0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 	u32 _unused1[0x1000/4 - 6];	/* padding */
111 	volatile u32 rx_cbptr;	 /* current dma buffer ptr, diagnostic use only */
113 	u32 _unused0[0x1000/4 - 2];	/* padding */
123 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
128 	volatile u32 rx_gfptr;	/* current GIO fifo ptr */
129 	volatile u32 rx_dfptr;	/* current device fifo ptr */
132 #define HPC3_ERST_CRESET 0x1	/* Reset dma channel and external controller */
133 #define HPC3_ERST_CLRIRQ 0x2	/* Clear channel interrupt */
152 	u32 _unused2[0x1000/4 - 8];	/* padding */
155 	volatile u32 tx_cbptr;	/* current dma buffer ptr, diagnostic use only */
157 	u32 _unused3[0x1000/4 - 2];	/* padding */
169 #define HPC3_ETXCTRL_ENDIAN 0x00000100	/* DMA channel endian mode, 1=little 0=big */
170 #define HPC3_ETXCTRL_ACTIVE 0x00000200	/* DMA tx channel is active */
173 	volatile u32 tx_gfptr;		/* current GIO fifo ptr */
174 	volatile u32 tx_dfptr;		/* current device fifo ptr */
175 	u32 _unused4[0x1000/4 - 4];	/* padding */
198 	 * you it was a peculiar bug. ;-)
201 #define HPC3_ISTAT_PBIMASK	0x0ff	/* irq bits for pbus devs 0 --> 7 */
202 #define HPC3_ISTAT_SC0MASK	0x100	/* irq bit for scsi channel 0 */
203 #define HPC3_ISTAT_SC1MASK	0x200	/* irq bit for scsi channel 1 */
221 #define HPC3_BESTAT_PIDMASK	0x3f700 /* DMA channel parity identifier */
223 	u32 _unused1[0x14000/4 - 5];	/* padding */
225 	/* Now direct PIO per-HPC3 peripheral access to external regs. */
226 	volatile u32 scsi0_ext[256];	/* SCSI channel 0 external regs */
228 	volatile u32 scsi1_ext[256];	/* SCSI channel 1 external regs */
233 	/* Per-peripheral device external registers and DMA/PIO control. */
254 	/* Enable 16-bit DMA access mode */
284 	/* Enable 16-bit PIO accesses */
293 	u32 _unused5[0x0800/4 - 1];
297 	u32 _unused6[0x0800/4 - 1];
301 	u32 _unused7[0x1000/4 - 1];
304 	volatile u32 bbram[8192-50-14]; /* Battery backed ram */