asm/sgi/hpc3.h

22 #define HPCDMA_EOX	0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR	0x80000000 /* last desc in chain for rx */
26 #define HPCDMA_XIE	0x20000000 /* irq generated when at end of this desc */
39 	volatile u32 pbdma_dptr;	/* pbus dma channel desc ptr */
40 	u32 _unused0[0x1000/4 - 2];	/* padding */
48 #define HPC3_PDMACTRL_SEL	0x00000002 /* little endian transfer */
54 #define HPC3_PDMACTRL_HW	0x0000ff00 /* DMA High-water mark */
58 	u32 _unused1[0x1000/4 - 1];	/* padding */
65 	u32 _unused0[0x1000/4 - 2];	/* padding */
73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
89 #define HPC3_SDCFG_HW	0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW	0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 	u32 _unused1[0x1000/4 - 6];	/* padding */
113 	u32 _unused0[0x1000/4 - 2];	/* padding */
123 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
140 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
152 	u32 _unused2[0x1000/4 - 8];	/* padding */
157 	u32 _unused3[0x1000/4 - 2];	/* padding */
161 #define HPC3_ETXBCD_XIE	    0x20000000	/* Interrupt cpu at end of cur desc */
163 #define HPC3_ETXBCD_EOX	    0x80000000	/* This buf is the end of desc chain */
169 #define HPC3_ETXCTRL_ENDIAN 0x00000100	/* DMA channel endian mode, 1=little 0=big */
175 	u32 _unused4[0x1000/4 - 4];	/* padding */
198 	 * you it was a peculiar bug. ;-)
201 #define HPC3_ISTAT_PBIMASK	0x0ff	/* irq bits for pbus devs 0 --> 7 */
207 #define HPC3_GIOMISC_DENDIAN	0x2	/* dma descriptor endian, 1=lit 0=big */
223 	u32 _unused1[0x14000/4 - 5];	/* padding */
225 	/* Now direct PIO per-HPC3 peripheral access to external regs. */
233 	/* Per-peripheral device external registers and DMA/PIO control. */
254 	/* Enable 16-bit DMA access mode */
284 	/* Enable 16-bit PIO accesses */
293 	u32 _unused5[0x0800/4 - 1];
297 	u32 _unused6[0x0800/4 - 1];
301 	u32 _unused7[0x1000/4 - 1];
304 	volatile u32 bbram[8192-50-14]; /* Battery backed ram */