Lines Matching +full:0 +full:x01000
24 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
47 * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49 * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
56 * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
58 * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
60 * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
62 * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
64 * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
79 struct ip30_heart_regs { /* 0x0ff00000 */
80 u64 mode; /* + 0x00000 */
82 u64 sdram_mode; /* + 0x00008 */
83 u64 mem_refresh; /* + 0x00010 */
84 u64 mem_req_arb; /* + 0x00018 */
88 } mem_cfg; /* + 0x00020 */
90 u64 fc_mode; /* + 0x00040 */
91 u64 fc_timer_limit; /* + 0x00048 */
92 u64 fc_addr[2]; /* + 0x00050 */
93 u64 fc_credit_cnt[2]; /* + 0x00060 */
94 u64 fc_timer[2]; /* + 0x00070 */
96 u64 status; /* + 0x00080 */
98 u64 bus_err_addr; /* + 0x00088 */
99 u64 bus_err_misc; /* + 0x00090 */
101 u64 mem_err_addr; /* + 0x00098 */
102 u64 mem_err_data; /* + 0x000a0 */
104 u64 piur_acc_err; /* + 0x000a8 */
105 u64 mlan_clock_div; /* + 0x000b0 */
106 u64 mlan_ctrl; /* + 0x000b8 */
107 u64 __pad0[0x01e8]; /* + 0x000c0 + 0x0f40 */
109 u64 undefined; /* + 0x01000 */
110 u64 __pad1[0x1dff]; /* + 0x01008 + 0xeff8 */
112 u64 imr[HEART_MAX_CPUS]; /* + 0x10000 */
113 u64 set_isr; /* + 0x10020 */
114 u64 clear_isr; /* + 0x10028 */
115 u64 isr; /* + 0x10030 */
116 u64 imsr; /* + 0x10038 */
117 u64 cause; /* + 0x10040 */
118 u64 __pad2[0x1ff7]; /* + 0x10048 + 0xffb8 */
120 u64 count; /* + 0x20000 */
121 u64 __pad3[0x1fff]; /* + 0x20008 + 0xfff8 */
122 u64 compare; /* + 0x30000 */
123 u64 __pad4[0x1fff]; /* + 0x30008 + 0xfff8 */
124 u64 trigger; /* + 0x40000 */
125 u64 __pad5[0x1fff]; /* + 0x40008 + 0xfff8 */
127 u64 cpuid; /* + 0x50000 */
128 u64 __pad6[0x1fff]; /* + 0x50008 + 0xfff8 */
129 u64 sync; /* + 0x60000 */
145 #define HEART_ATK_MASK 0x0007ffffffffffff /* HEART attack mask */
146 #define HEART_ACK_ALL_MASK 0xffffffffffffffff /* Ack everything */
147 #define HEART_CLR_ALL_MASK 0x0000000000000000 /* Clear all */
148 #define HEART_BR_ERR_MASK 0x7ff8000000000000 /* BRIDGE error mask */
149 #define HEART_CPU0_ERR_MASK 0x8ff8000000000000 /* CPU0 error mask */
150 #define HEART_CPU1_ERR_MASK 0x97f8000000000000 /* CPU1 error mask */
151 #define HEART_CPU2_ERR_MASK 0xa7f8000000000000 /* CPU2 error mask */
152 #define HEART_CPU3_ERR_MASK 0xc7f8000000000000 /* CPU3 error mask */
153 #define HEART_ERR_MASK 0x1ff /* HEART error mask */
159 #define HM_PROC_DISABLE_MSK (0xfUL << HM_PROC_DISABLE_SHFT)
160 #define HM_PROC_DISABLE(x) (0x1UL << (x) + HM_PROC_DISABLE_SHFT)
161 #define HM_MAX_PSR (0x7UL << 57)
162 #define HM_MAX_IOSR (0x7UL << 54)
163 #define HM_MAX_PEND_IOSR (0x7UL << 51)
164 #define HM_TRIG_SRC_SEL_MSK (0x7UL << 48)
165 #define HM_TRIG_HEART_EXC (0x0UL << 48)
166 #define HM_TRIG_REG_BIT (0x1UL << 48)
167 #define HM_TRIG_SYSCLK (0x2UL << 48)
168 #define HM_TRIG_MEMCLK_2X (0x3UL << 48)
169 #define HM_TRIG_MEMCLK (0x4UL << 48)
170 #define HM_TRIG_IOCLK (0x5UL << 48)
171 #define HM_PIU_TEST_MODE (0xfUL << 40)
172 #define HM_GP_FLAG_MSK (0xfUL << 36)
174 #define HM_MAX_PROC_HYST (0xfUL << 32)
203 #define HM_COR_MEM_ERE BIT(0)
206 #define HEART_MEMREF_REFS(x) ((0xfUL & (x)) << 16)
207 #define HEART_MEMREF_PERIOD(x) ((0xffffUL & (x)))
209 #define HEART_MEMREF_PERIOD_VAL HEART_MEMREF_PERIOD(0x4000)
222 #define HEART_MEMCFG_VALID 0x80000000 /* Bank is valid */
223 #define HEART_MEMCFG_DENSITY 0x01c00000 /* Mem density */
224 #define HEART_MEMCFG_SIZE_MASK 0x003f0000 /* Mem size mask */
225 #define HEART_MEMCFG_ADDR_MASK 0x000001ff /* Base addr mask */
238 #define HEART_STAT_PROC_MSK (0xfUL << HEART_STAT_PROC_SHFT)
239 #define HEART_STAT_PROC_ACTIVE(x) (0x1UL << ((x) + HEART_STAT_PROC_SHFT))
240 #define HEART_STAT_WIDGET_ID 0xf
243 #define HC_PE_SYS_COR_ERR_MSK (0xfUL << 60)
250 #define HC_SYSSTATE_ERR_MSK (0xfUL << 36)
252 #define HC_SYSCMD_ERR_MSK (0xfUL << 32)
254 #define HC_NCOR_SYSAD_ERR_MSK (0xfUL << 28)
256 #define HC_COR_SYSAD_ERR_MSK (0xfUL << 24)
258 #define HC_DATA_ELMNT_ERR_MSK (0xfUL << 20)
261 #define HC_MEM_ADDR_ERR_PROC_MSK (0xfUL << 4)
265 #define HC_COR_MEM_ERR BIT(0)
269 * priority levels. They are numbered 0 to 63.
281 * Level 0 - General device GFX flow control interrupts.
283 #define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */
284 #define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */
285 #define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */
286 #define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */
287 #define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */
290 #define HEART_L0_INT_GENERIC 0