asm/octeon/cvmx-l2c.h

7  * Copyright (c) 2003-2017 Cavium, Inc.
10  * it under the terms of the GNU General Public License, Version 2, as
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
44 #define CVMX_L2C_IDX_MASK	(cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
72 	CVMX_L2C_EVENT_INSTRUCTION_HIT	=  2,
131 	CVMX_L2C_TAD_EVENT_TAG_MISS	 = 2,
183  * Return the L2 Cache way partitioning for a given core.
189  *	      -1 on error
199  *	       a way, while a 1 bit blocks the core from evicting any
200  *	       lines from that way. There must be at least one allowed
201  *	       way (0 bit) in the mask.
212  * Return the L2 Cache way partitioning for the hw blocks.
214  * Returns    The mask specifying the reserved way. 0 bits in mask indicates
216  *	      -1 on error
225  *	       a way, while a 1 bit blocks the core from evicting any
226  *	       lines from that way. There must be at least one allowed
227  *	       way (0 bit) in the mask.
295  * @index:  Which way to read from.
331  * -1 on error (unrecognized model)
343  * Return log base 2 of the number of sets in the L2 cache
359  * @assoc:  Association (or way) to flush