Lines Matching +full:0 +full:x40c00000
44 * Coprocessor 0 register names
49 #define CP0_INDEX $0
50 #define C0_INDEX 0, 0
53 #define C0_RANDOM 1, 0
56 #define C0_ENTRYLO0 2, 0
59 #define C0_ENTRYLO1 3, 0
62 #define C0_CONF 3, 0
68 #define C0_CONTEXT 4, 0
71 #define C0_PAGEMASK 5, 0
95 #define C0_WIRED 6, 0
98 #define C0_INFO 7, 0
101 #define C0_HWRENA 7, 0
104 #define C0_BADVADDR 8, 0
113 #define C0_COUNT 9, 0
119 #define C0_ENTRYHI 10, 0
131 #define C0_COMPARE 11, 0
137 #define C0_STATUS 12, 0
146 #define C0_CAUSE 13, 0
149 #define C0_EPC 14, 0
152 #define C0_PRID 15, 0
161 #define C0_CONFIG 16, 0
182 #define C0_LLADDR 17, 0
185 #define C0_WATCHLO 18, 0
188 #define C0_WATCHHI 19, 0
191 #define C0_XCONTEXT 20, 0
194 #define C0_FRAMEMASK 21, 0
197 #define C0_DIAGNOSTIC 22, 0
203 #define C0_DEBUG 23, 0
206 #define C0_DEPC 24, 0
209 #define C0_PERFORMANCE 25, 0
212 #define C0_ECC 26, 0
215 #define C0_CACHEERR 27, 0
218 #define C0_TAGLO 28, 0
230 #define C0_TAGHI 29, 0
233 #define C0_ERROREPC 30, 0
236 #define C0_DESAVE 31, 0
244 #define CP0_IBASE $0
253 * Coprocessor 0 Set 1 register names
260 * Coprocessor 0 Set 2 register names
265 * Coprocessor 0 Set 3 register names
276 #define ENTRYLO_G (_ULCAST_(1) << 0)
296 #define MIPS_GLOBALNUMBER_VP_SHF 0
297 #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
299 #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
301 #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
306 #define PM_4K 0x00000000
307 #define PM_8K 0x00002000
308 #define PM_16K 0x00006000
309 #define PM_32K 0x0000e000
310 #define PM_64K 0x0001e000
311 #define PM_128K 0x0003e000
312 #define PM_256K 0x0007e000
313 #define PM_512K 0x000fe000
314 #define PM_1M 0x001fe000
315 #define PM_2M 0x003fe000
316 #define PM_4M 0x007fe000
317 #define PM_8M 0x00ffe000
318 #define PM_16M 0x01ffe000
319 #define PM_32M 0x03ffe000
320 #define PM_64M 0x07ffe000
321 #define PM_256M 0x1fffe000
322 #define PM_1G 0x7fffe000
362 #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
363 #define MIPSR6_WIRED_WIRED_SHIFT 0
364 #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
390 #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
391 #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
420 #define ST0_IE 0x00000001
421 #define ST0_EXL 0x00000002
422 #define ST0_ERL 0x00000004
423 #define ST0_KSU 0x00000018
424 # define KSU_USER 0x00000010
425 # define KSU_SUPERVISOR 0x00000008
426 # define KSU_KERNEL 0x00000000
427 #define ST0_UX 0x00000020
428 #define ST0_SX 0x00000040
429 #define ST0_KX 0x00000080
430 #define ST0_DE 0x00010000
431 #define ST0_CE 0x00020000
436 #define ST0_KX_IF_64 0
444 #define ST0_CO 0x08000000
449 #define ST0_IEC 0x00000001
450 #define ST0_KUC 0x00000002
451 #define ST0_IEP 0x00000004
452 #define ST0_KUP 0x00000008
453 #define ST0_IEO 0x00000010
454 #define ST0_KUO 0x00000020
456 #define ST0_ISC 0x00010000
457 #define ST0_SWC 0x00020000
458 #define ST0_CM 0x00080000
470 #define ST0_MX 0x01000000
475 #define ST0_IM 0x0000ff00
492 #define STATUSB_IP8 0
493 #define STATUSF_IP8 (_ULCAST_(1) << 0)
508 #define ST0_CH 0x00040000
509 #define ST0_NMI 0x00080000
510 #define ST0_SR 0x00100000
511 #define ST0_TS 0x00200000
512 #define ST0_BEV 0x00400000
513 #define ST0_RE 0x02000000
514 #define ST0_FR 0x04000000
515 #define ST0_CU 0xf0000000
516 #define ST0_CU0 0x10000000
517 #define ST0_CU1 0x20000000
518 #define ST0_CU2 0x40000000
519 #define ST0_CU3 0x80000000
520 #define ST0_XX 0x80000000 /* MIPS IV naming */
530 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
540 * Bitfields and bit numbers in the coprocessor 0 cause register.
584 #define EXCCODE_INT 0 /* Interrupt pending */
618 * Bits in the coprocessor 0 config register.
621 #define CONF_CM_CACHABLE_NO_WA 0
722 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
724 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
753 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
762 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
790 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
791 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
792 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
813 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
833 #define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
871 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
882 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
887 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
888 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
891 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
892 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
893 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
896 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
897 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
900 #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
906 #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
908 #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
909 #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
918 #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
920 #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
921 #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
922 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
937 #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
944 #define MIPS_MAARX_ADDR 0xF
948 #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
951 #define MIPS_EBASE_CPUNUM_SHIFT 0
952 #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
963 #define MIPS_LLADDR_LLB_SHIFT 0
975 #define MIPS_SEGCFG_C_SHIFT 0
984 #define MIPS_SEGCFG_UK _ULCAST_(0)
987 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
989 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
991 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
993 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
994 #define MIPS_PWFIELD_PTEI_SHIFT 0
995 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
998 #define MIPS_PWSIZE_PS_MASK 0x40000000
1000 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
1002 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
1004 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
1006 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
1007 #define MIPS_PWSIZE_PTEW_SHIFT 0
1008 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
1011 #define MIPS_PWCTL_PWEN_MASK 0x80000000
1013 #define MIPS_PWCTL_XK_MASK 0x10000000
1015 #define MIPS_PWCTL_XS_MASK 0x08000000
1017 #define MIPS_PWCTL_XU_MASK 0x04000000
1019 #define MIPS_PWCTL_DPH_MASK 0x00000080
1021 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
1022 #define MIPS_PWCTL_PSN_SHIFT 0
1023 #define MIPS_PWCTL_PSN_MASK 0x0000003f
1035 #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
1055 #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
1058 #define MIPS_GCTL0_SFC1_SHIFT 0
1066 #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
1076 #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
1078 #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
1087 #define MIPS_GCTL0EXT_MG_SHIFT 0
1091 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
1096 #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
1100 #define MIPS_GCTL1_ID_SHIFT 0
1102 #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
1105 #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
1108 #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
1111 #define MIPS_GCTL1_ROOT_GUESTID 0
1114 #define MIPS_CDMMBASE_SIZE_SHIFT 0
1122 #define MIPS_HWR_CPUNUM 0 /* CPU number */
1143 #define TX39_CONF_ICS_MASK 0x00380000
1144 #define TX39_CONF_ICS_1KB 0x00000000
1145 #define TX39_CONF_ICS_2KB 0x00080000
1146 #define TX39_CONF_ICS_4KB 0x00100000
1147 #define TX39_CONF_ICS_8KB 0x00180000
1148 #define TX39_CONF_ICS_16KB 0x00200000
1151 #define TX39_CONF_DCS_MASK 0x00070000
1152 #define TX39_CONF_DCS_1KB 0x00000000
1153 #define TX39_CONF_DCS_2KB 0x00010000
1154 #define TX39_CONF_DCS_4KB 0x00020000
1155 #define TX39_CONF_DCS_8KB 0x00030000
1156 #define TX39_CONF_DCS_16KB 0x00040000
1158 #define TX39_CONF_CWFON 0x00004000
1159 #define TX39_CONF_WBON 0x00002000
1161 #define TX39_CONF_RF_MASK 0x00000c00
1162 #define TX39_CONF_DOZE 0x00000200
1163 #define TX39_CONF_HALT 0x00000100
1164 #define TX39_CONF_LOCK 0x00000080
1165 #define TX39_CONF_ICE 0x00000020
1166 #define TX39_CONF_DCE 0x00000010
1168 #define TX39_CONF_IRSIZE_MASK 0x0000000c
1169 #define TX39_CONF_DRSIZE_SHIFT 0
1170 #define TX39_CONF_DRSIZE_MASK 0x00000003
1204 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1206 #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1214 #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1215 #define CVMVMCONF_RMMUSIZEM1_S 0
1216 #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1225 #define CP1_REVISION $0
1251 #define MIPS_FCCR_CONDX_S 0
1253 #define MIPS_FCCR_COND0_S 0
1282 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1303 * Bits 22:20 of the FPU Status Register will be read as 0,
1319 #define FPU_CSR_ALL_X 0x0003f000
1320 #define FPU_CSR_UNI_X 0x00020000
1321 #define FPU_CSR_INV_X 0x00010000
1322 #define FPU_CSR_DIV_X 0x00008000
1323 #define FPU_CSR_OVF_X 0x00004000
1324 #define FPU_CSR_UDF_X 0x00002000
1325 #define FPU_CSR_INE_X 0x00001000
1327 #define FPU_CSR_ALL_E 0x00000f80
1328 #define FPU_CSR_INV_E 0x00000800
1329 #define FPU_CSR_DIV_E 0x00000400
1330 #define FPU_CSR_OVF_E 0x00000200
1331 #define FPU_CSR_UDF_E 0x00000100
1332 #define FPU_CSR_INE_E 0x00000080
1334 #define FPU_CSR_ALL_S 0x0000007c
1335 #define FPU_CSR_INV_S 0x00000040
1336 #define FPU_CSR_DIV_S 0x00000020
1337 #define FPU_CSR_OVF_S 0x00000010
1338 #define FPU_CSR_UDF_S 0x00000008
1339 #define FPU_CSR_INE_S 0x00000004
1341 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1342 #define FPU_CSR_RM 0x00000003
1343 #define FPU_CSR_RN 0x0 /* nearest */
1344 #define FPU_CSR_RZ 0x1 /* towards zero */
1345 #define FPU_CSR_RU 0x2 /* towards +Infinity */
1346 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1356 #define get_isa16_mode(x) ((x) & 0x1)
1357 #define msk_isa16_mode(x) ((x) & ~0x1)
1358 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1360 #define get_isa16_mode(x) 0
1362 #define set_isa16_mode(x) do { } while(0)
1367 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1371 u16 opcode = (insn >> 10) & 0x7; in mm_insn_16bit()
1373 return (opcode >= 1 && opcode <= 3) ? 1 : 0; in mm_insn_16bit()
1386 ".hword ((" #_enc ") & 0xffff)\n\t"
1417 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1419 * "# di %0\n\t"
1420 * ".word (0x41606000 | (__rt << 16))"
1435 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) \
1499 ".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1516 _ASM_INSN_IF_MIPS(0x42000004) in tlbinvf()
1517 _ASM_INSN32_IF_MM(0x0000537c) in tlbinvf()
1526 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1527 * disassembler these will look like an access to sel 0 or 1.
1533 "mfpc\t%0, %1" \
1543 "mtpc\t%0, %1" \
1546 } while (0)
1552 "mfps\t%0, %1" \
1562 "mtps\t%0, %1" \
1565 } while (0)
1574 if (sel == 0) \
1576 "mfc0\t%0, " #source "\n\t" \
1582 "mfc0\t%0, " #source ", " #sel "\n\t" \
1592 else if (sel == 0) \
1596 "dmfc0\t%0, " #source "\n\t" \
1603 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1623 if (sel == 0) \
1634 } while (0)
1640 else if (sel == 0) \
1654 } while (0)
1672 } while (0)
1680 "cfc0\t%0, " #source "\n\t" \
1690 } while (0)
1702 if (sel == 0) \
1708 "sll\t%L0, %L0, 0\n\t" \
1717 "sll\t%L0, %L0, 0\n\t" \
1739 else if (sel == 0) \
1762 } while (0)
1767 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \
1768 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11))
1772 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \
1773 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
1790 " mfhc0 %0, " #source ", %1 \n" \
1809 } while (0)
1811 #define read_c0_index() __read_32bit_c0_register($0, 0)
1812 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1814 #define read_c0_random() __read_32bit_c0_register($1, 0)
1815 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1817 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1818 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1820 #define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1821 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1823 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1824 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1826 #define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1827 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1829 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1830 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1834 #define read_c0_context() __read_ulong_c0_register($4, 0)
1835 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1849 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1850 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1855 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1856 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1858 #define read_c0_info() __read_32bit_c0_register($7, 0)
1860 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1861 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1863 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1864 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1869 #define read_c0_count() __read_32bit_c0_register($9, 0)
1870 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1872 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1873 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1884 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1885 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1890 #define read_c0_status() __read_32bit_c0_register($12, 0)
1892 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1900 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1901 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1903 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1904 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1906 #define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1910 #define read_c0_config() __read_32bit_c0_register($16, 0)
1918 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1927 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1928 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1939 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1947 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1959 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1968 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1977 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1978 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1983 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1984 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1986 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1987 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1990 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1991 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
2008 #define read_c0_debug() __read_32bit_c0_register($23, 0)
2009 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
2011 #define read_c0_depc() __read_ulong_c0_register($24, 0)
2012 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
2017 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
2018 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
2042 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
2043 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
2048 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
2053 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
2054 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
2065 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
2066 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
2068 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
2069 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
2072 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
2073 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
2142 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
2143 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
2149 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
2150 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
2175 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2176 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2203 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \
2204 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2208 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) \
2209 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2213 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) \
2214 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2218 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) \
2219 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2223 _ASM_INSN_IF_MIPS(0x42000010) \
2224 _ASM_INSN32_IF_MM(0x0000017c)
2226 _ASM_INSN_IF_MIPS(0x42000009) \
2227 _ASM_INSN32_IF_MM(0x0000117c)
2229 _ASM_INSN_IF_MIPS(0x4200000a) \
2230 _ASM_INSN32_IF_MM(0x0000217c)
2232 _ASM_INSN_IF_MIPS(0x4200000e) \
2233 _ASM_INSN32_IF_MM(0x0000317c)
2235 _ASM_INSN_IF_MIPS(0x4200000c) \
2236 _ASM_INSN32_IF_MM(0x0000517c)
2267 "mfgc0\t%0, " #source ", %1\n\t" \
2280 "dmfgc0\t%0, " #source ", %1\n\t" \
2298 } while (0)
2310 } while (0)
2323 } while (0)
2325 #define read_gc0_index() __read_32bit_gc0_register($0, 0)
2326 #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2328 #define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2329 #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2331 #define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2332 #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2334 #define read_gc0_context() __read_ulong_gc0_register($4, 0)
2335 #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2346 #define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2347 #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2370 #define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2371 #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2376 #define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2377 #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2379 #define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2380 #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2388 #define read_gc0_count() __read_32bit_gc0_register($9, 0)
2390 #define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2391 #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2393 #define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2394 #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2396 #define read_gc0_status() __read_32bit_gc0_register($12, 0)
2397 #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2402 #define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2403 #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2405 #define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2406 #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2408 #define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2416 #define read_gc0_config() __read_32bit_gc0_register($16, 0)
2424 #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2433 #define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2434 #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2436 #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2444 #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2453 #define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2461 #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2470 #define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2471 #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2473 #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2474 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2498 #define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2499 #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2541 " cfc1 %0,"STR(source)" \n" \
2553 " ctc1 %0,"STR(dest)" \n" \
2556 } while (0)
2567 " rddsp %0, %x1 \n" \
2580 " wrdsp %0, %x1 \n" \
2584 } while (0)
2593 " mflo %0, $ac0 \n" \
2606 " mflo %0, $ac1 \n" \
2619 " mflo %0, $ac2 \n" \
2632 " mflo %0, $ac3 \n" \
2645 " mfhi %0, $ac0 \n" \
2658 " mfhi %0, $ac1 \n" \
2671 " mfhi %0, $ac2 \n" \
2684 " mfhi %0, $ac3 \n" \
2697 " mtlo %0, $ac0 \n" \
2709 " mtlo %0, $ac1 \n" \
2721 " mtlo %0, $ac2 \n" \
2733 " mtlo %0, $ac3 \n" \
2745 " mthi %0, $ac0 \n" \
2757 " mthi %0, $ac1 \n" \
2769 " mthi %0, $ac2 \n" \
2781 " mthi %0, $ac3 \n" \
2797 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2798 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2799 " move %0, $1 \n" \
2811 " move $1, %0 \n" \
2813 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2814 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2818 } while (0)
2827 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2828 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2829 " move %0, $1 \n" \
2841 " move $1, %0 \n" \
2842 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2843 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2847 } while (0)
2851 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2852 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2854 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2855 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2859 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2860 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2862 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2863 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2867 #define mflo0() _dsp_mflo(0)
2872 #define mfhi0() _dsp_mfhi(0)
2877 #define mtlo0(x) _dsp_mtlo(x, 0)
2882 #define mthi0(x) _dsp_mthi(x, 0)
2905 int res = 0; in tlb_read()
2912 " .word 0x41610001 # dvpe $1 \n" in tlb_read()
2913 " move %0, $1 \n" in tlb_read()
2933 " .word 0x41600021 # evpe \n" in tlb_read()