include/asm/mips-gic.h

20 #define MIPS_GIC_SHARED_OFS	0x00000
21 #define MIPS_GIC_SHARED_SZ	0x08000
22 #define MIPS_GIC_LOCAL_OFS	0x08000
23 #define MIPS_GIC_LOCAL_SZ	0x04000
24 #define MIPS_GIC_REDIR_OFS	0x0c000
25 #define MIPS_GIC_REDIR_SZ	0x04000
26 #define MIPS_GIC_USER_OFS	0x10000
27 #define MIPS_GIC_USER_SZ	0x10000
115 	return val & 0x1;						\
182 GIC_ACCESSOR_RW(32, 0x000, config)
186 #define GIC_CONFIG_PVPS			GENMASK(6, 0)
189 GIC_ACCESSOR_RW(64, 0x010, counter)
190 GIC_ACCESSOR_RW(32, 0x010, counter_32l)
191 GIC_ACCESSOR_RW(32, 0x014, counter_32h)
194 GIC_ACCESSOR_RW_INTR_BIT(0x100, pol)
195 #define GIC_POL_ACTIVE_LOW		0	/* when level triggered */
197 #define GIC_POL_FALLING_EDGE		0	/* when single-edge triggered */
201 GIC_ACCESSOR_RW_INTR_BIT(0x180, trig)
202 #define GIC_TRIG_LEVEL			0
206 GIC_ACCESSOR_RW_INTR_BIT(0x200, dual)
207 #define GIC_DUAL_SINGLE			0	/* when edge-triggered */
211 GIC_ACCESSOR_RW(32, 0x280, wedge)
213 #define GIC_WEDGE_INTR			GENMASK(7, 0)
216 GIC_ACCESSOR_RW_INTR_BIT(0x300, rmask)
219 GIC_ACCESSOR_RW_INTR_BIT(0x380, smask)
222 GIC_ACCESSOR_RO_INTR_BIT(0x400, mask)
225 GIC_ACCESSOR_RO_INTR_BIT(0x480, pend)
228 GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
231 #define GIC_MAP_PIN_MAP			GENMASK(5, 0)
234 GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
237 GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
242 #define GIC_VX_CTL_EIC			BIT(0)
245 GIC_VX_ACCESSOR_RO(32, 0x004, pend)
248 GIC_VX_ACCESSOR_RO(32, 0x008, mask)
251 GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
254 GIC_VX_ACCESSOR_RW(32, 0x010, smask)
257 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
260 GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
263 GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
266 GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
269 GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
272 GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
274 /* GIC_Vx_SWINT0_MAP - Route the local software interrupt 0 */
275 GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
278 GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
281 GIC_VX_ACCESSOR_RW(32, 0x080, other)
282 #define GIC_VX_OTHER_VPNUM		GENMASK(5, 0)
285 GIC_VX_ACCESSOR_RO(32, 0x088, ident)
286 #define GIC_VX_IDENT_VPNUM		GENMASK(5, 0)
289 GIC_VX_ACCESSOR_RW(64, 0x0a0, compare)
292 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)
300  * @GIC_LOCAL_INT_SWINT0: Software interrupt 0
364  * Determine the virq number to use for the coprocessor 0 count/compare