1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
18 /* The base address of the CM GCR block */
21 /* The base address of the CM L2-only sync region */
25  * mips_cm_phys_base - retrieve the physical base address of the CM
36  * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM
37  *                            L2-sync region
40  * L2-cache only region. It provides a default implementation which reads the
42  * behind the CM GCR base address. It may be overridden by platforms which
49  * mips_cm_is64 - determine CM register width
51  * The CM register width is determined by the version of the CM, with CM3
52  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
54  * or vice-versa. This variable indicates the width of the memory accesses
58  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
63  * mips_cm_error_report - Report CM cache errors
72  * mips_cm_probe - probe for a Coherence Manager
74  * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
75  * is successfully detected, else -errno.
82 	return -ENODEV;  in mips_cm_probe()
87  * mips_cm_present - determine whether a Coherence Manager is present
89  * Returns true if a CM is present in the system, else false.
101  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
103  * Returns true if the system implements an L2-only sync region, else false.
114 /* Offsets to register blocks from the CM base address */
120 /* Total size of the CM memory mapped registers */
123 /* Size of the L2-only sync region */
126 #define GCR_ACCESSOR_RO(sz, off, name)					\  argument
127 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
128 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
130 #define GCR_ACCESSOR_RW(sz, off, name)					\  argument
131 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
132 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
134 #define GCR_CX_ACCESSOR_RO(sz, off, name)				\  argument
135 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
136 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
138 #define GCR_CX_ACCESSOR_RW(sz, off, name)				\  argument
139 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
140 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
142 /* GCR_CONFIG - Information about the system */
150 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
159 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
163 /* GCR_REV - Indicates the Coherence Manager revision */
177 /* GCR_ERR_CONTROL - Control error checking logic */
182 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
185 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
191 /* GCR_ERR_ADDR - Indicates the address associated with an error */
194 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
198 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
203 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
208 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
213 /* GCR_REGn_BASE - Base addresses of CM address regions */
220 /* GCR_REGn_MASK - Size & destination of CM address regions */
235 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
239 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
243 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
247 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
254 /* GCR_SYS_CONFIG2 - Further information about the system */
258 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
264 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
269 /* GCR_L2SM_COP - L2 cache op state machine control */
291 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
296 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
299 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
302 /* GCR_Cx_COHERENCE - Controls core coherence */
307 /* GCR_Cx_CONFIG - Information about a core's configuration */
312 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
314 #define CM_GCR_Cx_OTHER_CORENUM			GENMASK(31, 16)	/* CM < 3 */
315 #define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
316 #define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
317 #define CM_GCR_Cx_OTHER_BLOCK			GENMASK(25, 24)	/* CM >= 3.5 */
322 #define CM_GCR_Cx_OTHER_CLUSTER			GENMASK(21, 16)	/* CM >= 3.5 */
323 #define CM3_GCR_Cx_OTHER_CORE			GENMASK(13, 8)	/* CM >= 3 */
325 #define CM3_GCR_Cx_OTHER_VP			GENMASK(2, 0)	/* CM >= 3 */
327 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
332 /* GCR_Cx_ID - Identify the current core */
337 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
346  * mips_cm_l2sync - perform an L2-only sync operation
348  * If an L2-only sync region is present in the system then this function
349  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
354 		return -ENODEV;  in mips_cm_l2sync()
361  * mips_cm_revision() - return CM revision
363  * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
375  * mips_cm_max_vp_width() - return the width in bits of VP indices
404  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
424  * mips_cm_lock_other - lock access to redirect/other region
431  * the CM revision) to target the specified @cluster, @core, @vp & register
437  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
445  * mips_cm_unlock_other - unlock access to redirect/other region
461  * mips_cm_lock_other_cpu - lock access to redirect/other region
465  * the CM revision) to target the specified @cpu & register @block. This is