Lines Matching +full:0 +full:x000000ff

33 #define ETH0_BASE_ADDR		0x18060000
84 #define ETH_INT_FC_EN		(1 << 0)
90 #define ETH_INT_FC_IOC		0x000000c0
93 #define ETH_FIFI_TT_TTH_BIT	0
94 #define ETH_FIFO_TT_TTH		0x0000007f
97 #define ETH_ARC_PRO		(1 << 0)
103 #define ETH_SAL_BYTE_5		0x000000ff
104 #define ETH_SAL_BYTE_4		0x0000ff00
105 #define ETH_SAL_BYTE_3		0x00ff0000
106 #define ETH_SAL_BYTE_2		0xff000000
109 #define ETH_SAH_BYTE1		0x000000ff
110 #define ETH_SAH_BYTE0		0x0000ff00
113 #define ETH_GPF_PTV		0x0000ffff
116 #define ETH_PFS_PFD		(1 << 0)
118 /* Ethernet CFSA[0-3] registers */
119 #define ETH_CFSA0_CFSA4		0x000000ff
120 #define ETH_CFSA0_CFSA5		0x0000ff00
121 #define ETH_CFSA1_CFSA2		0x000000ff
122 #define ETH_CFSA1_CFSA3		0x0000ff00
123 #define ETH_CFSA1_CFSA0		0x000000ff
124 #define ETH_CFSA1_CFSA1		0x0000ff00
127 #define ETH_MAC1_RE		(1 << 0)
135 #define ETH_MAC2_FD		(1 << 0)
150 #define ETH_IPGT		0x0000007f
153 #define ETH_IPGR_IPGR2		0x0000007f
154 #define ETH_IPGR_IPGR1		0x00007f00
157 #define ETH_CLRT_MAX_RET	0x0000000f
158 #define ETH_CLRT_COL_WIN	0x00003f00
161 #define ETH_MAXF		0x0000ffff
165 #define ETH_MCP_DIV		0x000000ff
168 #define ETH_MII_CFG_RSVD	0x0000000c
169 #define ETH_MII_CMD_RD		(1 << 0)
171 #define ETH_MII_REG_ADDR	0x0000001f
172 #define ETH_MII_PHY_ADDR	0x00001f00
173 #define ETH_MII_WTD_DATA	0x0000ffff
174 #define ETH_MII_RDD_DATA	0x0000ffff
175 #define ETH_MII_IND_BSY		(1 << 0)
183 #define ETH_RX_FD		(1 << 0)
199 #define ETH_RX_LEN		0xffff0000
201 #define ETH_TX_FD		(1 << 0)
218 #define ETH_TX_CC		0x001E0000