Lines Matching +full:0 +full:xee00
10 #define PERF_REV_REG 0x0
12 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
13 #define REV_REVID_SHIFT 0
14 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
17 #define PERF_CKCTL_REG 0x4
52 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
76 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
92 * specific BCM6345 code for handling clocks, and writing 0 to the test
107 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
214 #define PERF_SYS_PLL_CTL_REG 0x8
215 #define SYS_PLL_SOFT_RESET 0x1
218 #define PERF_IRQMASK_3368_REG 0xc
219 #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
220 #define PERF_IRQMASK_6338_REG 0xc
221 #define PERF_IRQMASK_6345_REG 0xc
222 #define PERF_IRQMASK_6348_REG 0xc
223 #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
224 #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
225 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
228 #define PERF_IRQSTAT_3368_REG 0x10
229 #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
230 #define PERF_IRQSTAT_6338_REG 0x10
231 #define PERF_IRQSTAT_6345_REG 0x10
232 #define PERF_IRQSTAT_6348_REG 0x10
233 #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
234 #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
235 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
238 #define PERF_EXTIRQ_CFG_REG_3368 0x14
239 #define PERF_EXTIRQ_CFG_REG_6328 0x18
240 #define PERF_EXTIRQ_CFG_REG_6338 0x14
241 #define PERF_EXTIRQ_CFG_REG_6345 0x14
242 #define PERF_EXTIRQ_CFG_REG_6348 0x14
243 #define PERF_EXTIRQ_CFG_REG_6358 0x14
244 #define PERF_EXTIRQ_CFG_REG_6362 0x18
245 #define PERF_EXTIRQ_CFG_REG_6368 0x18
247 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
256 #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
257 #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
266 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
267 #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
270 #define PERF_SOFTRESET_REG 0x28
271 #define PERF_SOFTRESET_6328_REG 0x10
272 #define PERF_SOFTRESET_6358_REG 0x34
273 #define PERF_SOFTRESET_6362_REG 0x10
274 #define PERF_SOFTRESET_6368_REG 0x10
276 #define SOFTRESET_3368_SPI_MASK (1 << 0)
283 #define SOFTRESET_6328_SPI_MASK (1 << 0)
295 #define SOFTRESET_6338_SPI_MASK (1 << 0)
314 #define SOFTRESET_6348_SPI_MASK (1 << 0)
334 #define SOFTRESET_6358_SPI_MASK (1 << 0)
343 #define SOFTRESET_6362_SPI_MASK (1 << 0)
359 #define SOFTRESET_6368_SPI_MASK (1 << 0)
369 #define PERF_MIPSPLLCTL_REG 0x34
371 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
373 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
375 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
377 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
379 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
381 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
382 #define MIPSPLLCTL_M2BUS_SHIFT 0
383 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
386 #define PERF_ADSLPLLCTL_REG 0x38
388 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
390 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
392 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
394 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
396 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
398 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
399 #define ADSLPLLCTL_M2BUS_SHIFT 0
400 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
417 #define TIMER_T0_ID 0
423 #define TIMER_IRQSTAT_REG 0
425 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
435 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
436 #define TIMER_CTL0_REG 0x4
437 #define TIMER_CTL1_REG 0x8
438 #define TIMER_CTL2_REG 0xC
439 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
449 #define WDT_DEFVAL_REG 0x0
452 #define WDT_CTL_REG 0x4
455 #define WDT_START_1 (0xff00)
456 #define WDT_START_2 (0x00ff)
457 #define WDT_STOP_1 (0xee00)
458 #define WDT_STOP_2 (0x00ee)
461 #define WDT_RSTLEN_REG 0x8
464 #define WDT_SOFTRESET_REG 0xc
471 #define GPIO_CTL_HI_REG 0x0
472 #define GPIO_CTL_LO_REG 0x4
473 #define GPIO_DATA_HI_REG 0x8
474 #define GPIO_DATA_LO_REG 0xC
475 #define GPIO_DATA_LO_REG_6345 0x8
478 #define GPIO_MODE_REG 0x18
480 #define GPIO_MODE_6348_G4_DIAG 0x00090000
481 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
482 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
483 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
484 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
485 #define GPIO_MODE_6348_G3_DIAG 0x00009000
486 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
487 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
488 #define GPIO_MODE_6348_G2_DIAG 0x00000900
489 #define GPIO_MODE_6348_G2_PCI 0x00000500
490 #define GPIO_MODE_6348_G1_DIAG 0x00000090
491 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
492 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
493 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
494 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
495 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
496 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
497 #define GPIO_MODE_6348_G0_DIAG 0x00000009
498 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
506 #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
539 #define GPIO_PINMUX_OTHR_REG 0x24
545 #define GPIO_BASEMODE_6368_REG 0x38
546 #define GPIO_BASEMODE_6368_UART2 0x1
547 #define GPIO_BASEMODE_6368_GPIO 0x0
548 #define GPIO_BASEMODE_6368_MASK 0x7
551 #define GPIO_STRAPBUS_REG 0x40
553 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
554 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
555 #define STRAPBUS_6368_BOOT_SEL_NAND 0
565 #define ENET_RXCFG_REG 0x0
576 #define ENET_RXMAXLEN_REG 0x4
577 #define ENET_RXMAXLEN_SHIFT 0
578 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
581 #define ENET_TXMAXLEN_REG 0x8
582 #define ENET_TXMAXLEN_SHIFT 0
583 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
586 #define ENET_MIISC_REG 0x10
587 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
588 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
593 #define ENET_MIIDATA_REG 0x14
594 #define ENET_MIIDATA_DATA_SHIFT 0
595 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
597 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
599 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
601 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
602 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
603 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
606 #define ENET_IRMASK_REG 0x18
609 #define ENET_IR_REG 0x1c
610 #define ENET_IR_MII (1 << 0)
615 #define ENET_CTL_REG 0x2c
616 #define ENET_CTL_ENABLE_SHIFT 0
626 #define ENET_TXCTL_REG 0x30
627 #define ENET_TXCTL_FD_SHIFT 0
631 #define ENET_TXWMARK_REG 0x34
632 #define ENET_TXWMARK_WM_SHIFT 0
633 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
636 #define ENET_MIBCTL_REG 0x38
637 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
641 #define ENET_PML_REG(x) (0x58 + (x) * 8)
642 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
647 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
654 #define ENETDMA_CHAN_WIDTH 0x10
655 #define ENETDMA_6345_CHAN_WIDTH 0x40
658 #define ENETDMA_CFG_REG (0x0)
659 #define ENETDMA_CFG_EN_SHIFT 0
664 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
667 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
670 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
675 #define ENETDMA_GLB_IRQSTAT_REG (0x40)
678 #define ENETDMA_GLB_IRQMASK_REG (0x44)
681 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
682 #define ENETDMA_CHANCFG_EN_SHIFT 0
688 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
689 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
694 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
697 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
700 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
703 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
706 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
709 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
712 #define ENETDMA_6345_CHANCFG_REG (0x00)
714 #define ENETDMA_6345_MAXBURST_REG (0x04)
716 #define ENETDMA_6345_RSTART_REG (0x08)
718 #define ENETDMA_6345_LEN_REG (0x0C)
720 #define ENETDMA_6345_IR_REG (0x14)
722 #define ENETDMA_6345_IRMASK_REG (0x18)
724 #define ENETDMA_6345_FC_REG (0x1C)
726 #define ENETDMA_6345_BUFALLOC_REG (0x20)
736 #define ENETDMAC_CHANCFG_REG (0x0)
737 #define ENETDMAC_CHANCFG_EN_SHIFT 0
751 #define ENETDMAC_IR_REG (0x4)
752 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
757 #define ENETDMAC_IRMASK_REG (0x8)
760 #define ENETDMAC_MAXBURST_REG (0xc)
768 #define ENETDMAS_RSTART_REG (0x0)
771 #define ENETDMAS_SRAM2_REG (0x4)
774 #define ENETDMAS_SRAM3_REG (0x8)
777 #define ENETDMAS_SRAM4_REG (0xc)
785 #define ENETSW_PTCTRL_REG(x) (0x0 + (x))
786 #define ENETSW_PTCTRL_RXDIS_MASK (1 << 0)
790 #define ENETSW_SWMODE_REG (0xb)
794 #define ENETSW_IMPOV_REG (0xe)
801 #define ENETSW_IMPOV_LINKUP_MASK (1 << 0)
804 #define ENETSW_PORTOV_REG(x) (0x58 + (x))
811 #define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
814 #define ENETSW_MDIOC_REG (0xb0)
822 #define ENETSW_MDIOD_REG (0xb4)
825 #define ENETSW_GMCR_REG (0x200)
826 #define ENETSW_GMCR_RST_MIB_MASK (1 << 0)
829 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
833 #define ENETSW_JMBCTL_PORT_REG (0x4004)
836 #define ENETSW_JMBCTL_MAXSIZE_REG (0x4008)
843 #define OHCI_PRIV_REG 0x0
844 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
854 #define USBH_PRIV_SWAP_6358_REG 0x0
855 #define USBH_PRIV_SWAP_6368_REG 0x1c
865 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
868 #define USBH_PRIV_UTMI_CTL_6368_REG 0x10
870 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
871 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
872 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
874 #define USBH_PRIV_TEST_6358_REG 0x24
875 #define USBH_PRIV_TEST_6368_REG 0x14
877 #define USBH_PRIV_SETUP_6368_REG 0x28
887 #define USBD_CONTROL_REG 0x00
895 #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
900 #define USBD_CONTROL_DONE_CSRS_SHIFT 0
904 #define USBD_STRAPS_REG 0x04
917 #define USBD_STRAPS_SPEED_SHIFT 0
921 #define USBD_STALL_REG 0x08
926 #define USBD_STALL_EPNUM_SHIFT 0
927 #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
930 #define USBD_STATUS_REG 0x0c
932 #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
936 #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
938 #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
939 #define USBD_STATUS_CFG_SHIFT 0
940 #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
943 #define USBD_EVENTS_REG 0x10
948 #define USBD_EVENT_IRQ_STATUS_REG 0x14
951 #define USBD_EVENT_IRQ_CFG_HI_REG 0x18
953 #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
955 #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
957 #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
961 #define USBD_EVENT_IRQ_MASK_REG 0x20
974 #define USBD_EVENT_IRQ_USB_RESET 0
977 #define USBD_TXFIFO_CONFIG_REG 0x40
979 #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
980 #define USBD_TXFIFO_CONFIG_START_SHIFT 0
981 #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
984 #define USBD_RXFIFO_CONFIG_REG 0x44
986 #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
987 #define USBD_RXFIFO_CONFIG_START_SHIFT 0
988 #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
991 #define USBD_TXFIFO_EPSIZE_REG 0x48
994 #define USBD_RXFIFO_EPSIZE_REG 0x4c
997 #define USBD_EPNUM_TYPEMAP_REG 0x50
999 #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
1000 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
1001 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
1004 #define USBD_CSR_SETUPADDR_REG 0x80
1005 #define USBD_CSR_SETUPADDR_DEF 0xb550
1007 #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
1009 #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
1011 #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
1013 #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
1015 #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
1020 #define USBD_CSR_EP_LOG_SHIFT 0
1021 #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
1034 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
1036 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
1037 #define MPI_CSBASE_SIZE_SHIFT 0
1038 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
1040 #define MPI_CSBASE_SIZE_8K 0
1058 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
1059 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
1061 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
1067 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
1069 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
1072 #define MPI_SP0_RANGE_REG 0x100
1073 #define MPI_SP0_REMAP_REG 0x104
1074 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
1075 #define MPI_SP1_RANGE_REG 0x10C
1076 #define MPI_SP1_REMAP_REG 0x110
1077 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
1079 #define MPI_L2PCFG_REG 0x11C
1080 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
1081 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
1083 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
1085 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
1087 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
1091 #define MPI_L2PMEMRANGE1_REG 0x120
1092 #define MPI_L2PMEMBASE1_REG 0x124
1093 #define MPI_L2PMEMREMAP1_REG 0x128
1094 #define MPI_L2PMEMRANGE2_REG 0x12C
1095 #define MPI_L2PMEMBASE2_REG 0x130
1096 #define MPI_L2PMEMREMAP2_REG 0x134
1097 #define MPI_L2PIORANGE_REG 0x138
1098 #define MPI_L2PIOBASE_REG 0x13C
1099 #define MPI_L2PIOREMAP_REG 0x140
1100 #define MPI_L2P_BASE_MASK (0xffff8000)
1101 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
1104 #define MPI_PCIMODESEL_REG 0x144
1105 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
1109 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
1111 #define MPI_LOCBUSCTL_REG 0x14C
1112 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
1115 #define MPI_LOCINT_REG 0x150
1123 #define MPI_PCICFGCTL_REG 0x178
1125 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
1128 #define MPI_PCICFGDATA_REG 0x17C
1131 #define BCMPCI_REG_TIMERS 0x40
1132 #define REG_TIMER_TRDY_SHIFT 0
1133 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
1135 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
1142 #define PCMCIA_C1_REG 0x0
1143 #define PCMCIA_C1_CD1_MASK (1 << 0)
1150 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
1156 #define PCMCIA_C2_REG 0x8
1157 #define PCMCIA_C2_DATA16_MASK (1 << 0)
1160 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
1162 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
1164 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
1166 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
1173 #define SDRAM_CFG_REG 0x0
1175 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
1177 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
1183 #define SDRAM_MBASE_REG 0xc
1185 #define SDRAM_PRIO_REG 0x2C
1198 #define MEMC_CFG_REG 0x4
1202 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
1204 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
1211 #define DDR_CSEND_REG 0x8
1213 #define DDR_DMIPSPLLCFG_REG 0x18
1214 #define DMIPSPLLCFG_M1_SHIFT 0
1215 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
1217 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
1219 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
1221 #define DDR_DMIPSPLLCFG_6368_REG 0x20
1222 #define DMIPSPLLCFG_6368_P1_SHIFT 0
1223 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1225 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1227 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1229 #define DDR_DMIPSPLLDIV_6368_REG 0x24
1230 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
1231 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1238 #define M2M_RX 0
1241 #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
1242 #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
1243 #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
1245 #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
1246 #define M2M_CTRL_ENABLE_MASK (1 << 0)
1255 #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
1256 #define M2M_STAT_DONE (1 << 0)
1259 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
1260 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
1267 #define SPI_6348_CMD 0x00 /* 16-bits register */
1268 #define SPI_6348_INT_STATUS 0x02
1269 #define SPI_6348_INT_MASK_ST 0x03
1270 #define SPI_6348_INT_MASK 0x04
1271 #define SPI_6348_ST 0x05
1272 #define SPI_6348_CLK_CFG 0x06
1273 #define SPI_6348_FILL_BYTE 0x07
1274 #define SPI_6348_MSG_TAIL 0x09
1275 #define SPI_6348_RX_TAIL 0x0b
1276 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1278 #define SPI_6348_MSG_DATA 0x41
1279 #define SPI_6348_MSG_DATA_SIZE 0x3f
1280 #define SPI_6348_RX_DATA 0x80
1281 #define SPI_6348_RX_DATA_SIZE 0x3f
1284 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1286 #define SPI_6358_MSG_DATA 0x02
1287 #define SPI_6358_MSG_DATA_SIZE 0x21e
1288 #define SPI_6358_RX_DATA 0x400
1289 #define SPI_6358_RX_DATA_SIZE 0x220
1290 #define SPI_6358_CMD 0x700 /* 16-bits register */
1291 #define SPI_6358_INT_STATUS 0x702
1292 #define SPI_6358_INT_MASK_ST 0x703
1293 #define SPI_6358_INT_MASK 0x704
1294 #define SPI_6358_ST 0x705
1295 #define SPI_6358_CLK_CFG 0x706
1296 #define SPI_6358_FILL_BYTE 0x707
1297 #define SPI_6358_MSG_TAIL 0x709
1298 #define SPI_6358_RX_TAIL 0x70B
1303 #define SPI_FD_RW 0x00
1304 #define SPI_HD_W 0x01
1305 #define SPI_HD_R 0x02
1306 #define SPI_BYTE_CNT_SHIFT 0
1311 #define SPI_CMD_NOOP 0x00
1312 #define SPI_CMD_SOFT_RESET 0x01
1313 #define SPI_CMD_HARD_RESET 0x02
1314 #define SPI_CMD_START_IMMEDIATE 0x03
1315 #define SPI_CMD_COMMAND_SHIFT 0
1316 #define SPI_CMD_COMMAND_MASK 0x000f
1321 #define SPI_DEV_ID_0 0
1327 #define SPI_INTR_CMD_DONE 0x01
1328 #define SPI_INTR_RX_OVERFLOW 0x02
1329 #define SPI_INTR_TX_UNDERFLOW 0x04
1330 #define SPI_INTR_TX_OVERFLOW 0x08
1331 #define SPI_INTR_RX_UNDERFLOW 0x10
1332 #define SPI_INTR_CLEAR_ALL 0x1f
1335 #define SPI_RX_EMPTY 0x02
1336 #define SPI_CMD_BUSY 0x04
1337 #define SPI_SERIAL_BUSY 0x08
1340 #define SPI_CLK_20MHZ 0x00
1341 #define SPI_CLK_0_391MHZ 0x01
1342 #define SPI_CLK_0_781MHZ 0x02 /* default */
1343 #define SPI_CLK_1_563MHZ 0x03
1344 #define SPI_CLK_3_125MHZ 0x04
1345 #define SPI_CLK_6_250MHZ 0x05
1346 #define SPI_CLK_12_50MHZ 0x06
1347 #define SPI_CLK_MASK 0x07
1348 #define SPI_SSOFFTIME_MASK 0x38
1350 #define SPI_BYTE_SWAP 0x80
1355 #define MISC_SERDES_CTRL_6328_REG 0x0
1356 #define MISC_SERDES_CTRL_6362_REG 0x4
1357 #define SERDES_PCIE_EN (1 << 0)
1360 #define MISC_STRAPBUS_6362_REG 0x14
1363 #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
1365 #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
1367 #define MISC_STRAPBUS_6328_REG 0x240
1369 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1371 #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18)
1377 #define PCIE_CONFIG2_REG 0x408
1379 #define CONFIG2_BAR1_SIZE_MASK 0xf
1381 #define PCIE_IDVAL3_REG 0x43c
1382 #define IDVAL3_CLASS_CODE_MASK 0xffffff
1384 #define PCIE_DLSTATUS_REG 0x1048
1387 #define PCIE_BRIDGE_OPT1_REG 0x2820
1393 #define PCIE_BRIDGE_OPT2_REG 0x2824
1398 #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1400 #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1401 #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1402 #define BASEMASK_REMAP_EN (1 << 0)
1405 #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1407 #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1409 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1410 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1412 #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1414 #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1415 #define PCIE_RC_INT_A (1 << 0)
1420 #define PCIE_DEVICE_OFFSET 0x8000
1426 #define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)