12 #include <asm/mach-au1x00/au1000.h>
15  * GPIO0-31 from GPIO1 block,	GPIO200-215 from GPIO2 block.
22 #define ALCHEMY_GPIO1_MAX	(ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX	(ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
47 	return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);  in au1000_gpio1_to_irq()
52 	return -ENXIO;  in au1000_gpio2_to_irq()
58 		return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;  in au1000_irq_to_gpio()
60 	return -ENXIO;  in au1000_irq_to_gpio()
65 	gpio -= ALCHEMY_GPIO1_BASE;  in au1500_gpio1_to_irq()
73 	return -ENXIO;  in au1500_gpio1_to_irq()
78 	gpio -= ALCHEMY_GPIO2_BASE;  in au1500_gpio2_to_irq()
81 	case 0 ... 3:	return MAKE_IRQ(1, 16 + gpio - 0);  in au1500_gpio2_to_irq()
82 	case 4 ... 5:	return MAKE_IRQ(1, 21 + gpio - 4);  in au1500_gpio2_to_irq()
83 	case 6 ... 7:	return MAKE_IRQ(1, 29 + gpio - 6);  in au1500_gpio2_to_irq()
86 	return -ENXIO;  in au1500_gpio2_to_irq()
95 		return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;  in au1500_irq_to_gpio()
97 		return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;  in au1500_irq_to_gpio()
99 		return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;  in au1500_irq_to_gpio()
101 		return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;  in au1500_irq_to_gpio()
106 	return -ENXIO;  in au1500_irq_to_gpio()
111 	return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);  in au1100_gpio1_to_irq()
116 	gpio -= ALCHEMY_GPIO2_BASE;  in au1100_gpio2_to_irq()
121 	return -ENXIO;  in au1100_gpio2_to_irq()
128 		return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;  in au1100_irq_to_gpio()
133 	return -ENXIO;  in au1100_irq_to_gpio()
138 	gpio -= ALCHEMY_GPIO1_BASE;  in au1550_gpio1_to_irq()
143 	case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);  in au1550_gpio1_to_irq()
146 	return -ENXIO;  in au1550_gpio1_to_irq()
151 	gpio -= ALCHEMY_GPIO2_BASE;  in au1550_gpio2_to_irq()
156 	case 6 ... 7:	return MAKE_IRQ(1, 29 + gpio - 6);  in au1550_gpio2_to_irq()
160 	return -ENXIO;  in au1550_gpio2_to_irq()
167 		return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;  in au1550_irq_to_gpio()
170 		return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;  in au1550_irq_to_gpio()
172 		return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;  in au1550_irq_to_gpio()
174 		return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;  in au1550_irq_to_gpio()
177 	return -ENXIO;  in au1550_irq_to_gpio()
182 	return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);  in au1200_gpio1_to_irq()
187 	gpio -= ALCHEMY_GPIO2_BASE;  in au1200_gpio2_to_irq()
190 	case 0 ... 2:	return MAKE_IRQ(0, 5 + gpio - 0);  in au1200_gpio2_to_irq()
192 	case 4 ... 7:	return MAKE_IRQ(0, 24 + gpio - 4);  in au1200_gpio2_to_irq()
196 	return -ENXIO;  in au1200_gpio2_to_irq()
203 		return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;  in au1200_irq_to_gpio()
205 		return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;  in au1200_irq_to_gpio()
209 		return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;  in au1200_irq_to_gpio()
212 	return -ENXIO;  in au1200_irq_to_gpio()
220 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);  in alchemy_gpio1_set_value()
227 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);  in alchemy_gpio1_get_value()
233 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);  in alchemy_gpio1_direction_input()
266 	return -ENXIO;  in alchemy_gpio1_to_irq()
269 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
271  * register enables use of GPIOs as wake source.
287 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);  in __alchemy_gpio2_mod_dir()
302 	mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);  in alchemy_gpio2_set_value()
311 				(1 << (gpio - ALCHEMY_GPIO2_BASE));  in alchemy_gpio2_get_value()
352 	return -ENXIO;  in alchemy_gpio2_to_irq()
372  * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
375  * GPIO208-215 have one shared interrupt line to the INTC.  They are
376  * and'ed with a per-pin enable bit and finally or'ed together to form
377  * a single irq request (useful for active-high sources).
378  * With this function, a pins' individual contribution to the int request
379  * can be enabled.  As with all other GPIO-based interrupts, the INTC
382  * NOTE: Calling this macro is only necessary for GPIO208-215; all other
383  * GPIO2-based interrupts have their own request to the INTC.  Please
386  * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
391  * (200-215 by default). No sanity checks are made,
397 	gpio2 -= ALCHEMY_GPIO2_BASE;  in alchemy_gpio2_enable_int()
399 	/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */  in alchemy_gpio2_enable_int()
403 		gpio2 -= 8;  in alchemy_gpio2_enable_int()
412  * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
421 	gpio2 -= ALCHEMY_GPIO2_BASE;  in alchemy_gpio2_disable_int()
423 	/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */  in alchemy_gpio2_disable_int()
427 		gpio2 -= 8;  in alchemy_gpio2_disable_int()
436  * alchemy_gpio2_enable -  Activate GPIO2 block.
451  * alchemy_gpio2_disable - disable GPIO2 block.
453  * Disable and put GPIO2 block in low-power mode.
464 /* wrappers for on-chip gpios; can be used before gpio chips have been
524 	return -ENXIO;  in alchemy_irq_to_gpio()