Lines Matching +full:0 +full:x07ffffff
50 #define DDMA_CONFIG_AL (1 << 0)
60 u32 ddma_irq; /* If bit 0 set, interrupt pending */
75 #define DDMA_CFG_EN (1 << 0) /* Channel enable */
82 #define DDMA_IRQ_IN (1 << 0)
86 #define DDMA_STAT_H (1 << 0) /* Channel Halted */
112 #define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
113 #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
114 #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
115 #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
116 #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
117 #define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */
118 #define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
119 #define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
120 #define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */
121 #define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */
122 #define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */
123 #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
124 #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
126 #define SW_STATUS_INUSE (1 << 0)
128 /* Command 0 device IDs. */
129 #define AU1550_DSCR_CMD0_UART0_TX 0
158 #define AU1200_DSCR_CMD0_UART0_TX 0
186 #define AU1300_DSCR_CMD0_UART0_TX 0
221 #define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
222 ((d) & 0xFF))
223 #define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
225 #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
226 #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
229 #define DSCR_CMD0_BYTE 0
233 #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
234 #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
237 #define DSCR_CMD0_STANDARD 0
241 #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
244 #define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
249 #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
252 #define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
253 #define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
254 #define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
255 #define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
258 #define DSCR_CMD1_FL_MEM_STRIDE0 0
262 #define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
267 #define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
268 #define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
269 #define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
270 #define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
275 #define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
276 #define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
277 #define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */
278 #define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
280 #define DSCR_xTS_SIZE1 0
287 #define DSCR_xAM_INCREMENT 0
295 #define DSCR_NXTPTR_MASK (0x07ffffff)
333 #define DEV_FLAGS_INUSE (1 << 0)
384 #define DDMA_FLAGS_IE (1 << 0)