Lines Matching +full:0 +full:x12000000
19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
29 #define AR71XX_SPI_SIZE 0x01000000
31 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
32 #define AR71XX_DDR_CTRL_SIZE 0x100
33 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
34 #define AR71XX_UART_SIZE 0x100
35 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
36 #define AR71XX_USB_CTRL_SIZE 0x100
37 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
38 #define AR71XX_GPIO_SIZE 0x100
39 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
40 #define AR71XX_PLL_SIZE 0x100
41 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42 #define AR71XX_RESET_SIZE 0x100
43 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
44 #define AR71XX_MII_SIZE 0x100
46 #define AR71XX_PCI_MEM_BASE 0x10000000
47 #define AR71XX_PCI_MEM_SIZE 0x07000000
49 #define AR71XX_PCI_WIN0_OFFS 0x10000000
50 #define AR71XX_PCI_WIN1_OFFS 0x11000000
51 #define AR71XX_PCI_WIN2_OFFS 0x12000000
52 #define AR71XX_PCI_WIN3_OFFS 0x13000000
53 #define AR71XX_PCI_WIN4_OFFS 0x14000000
54 #define AR71XX_PCI_WIN5_OFFS 0x15000000
55 #define AR71XX_PCI_WIN6_OFFS 0x16000000
56 #define AR71XX_PCI_WIN7_OFFS 0x07000000
59 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
60 #define AR71XX_PCI_CFG_SIZE 0x100
62 #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
63 #define AR7240_USB_CTRL_SIZE 0x100
64 #define AR7240_OHCI_BASE 0x1b000000
65 #define AR7240_OHCI_SIZE 0x1000
67 #define AR724X_PCI_MEM_BASE 0x10000000
68 #define AR724X_PCI_MEM_SIZE 0x04000000
70 #define AR724X_PCI_CFG_BASE 0x14000000
71 #define AR724X_PCI_CFG_SIZE 0x1000
72 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
73 #define AR724X_PCI_CRP_SIZE 0x1000
74 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
75 #define AR724X_PCI_CTRL_SIZE 0x100
77 #define AR724X_EHCI_BASE 0x1b000000
78 #define AR724X_EHCI_SIZE 0x1000
80 #define AR913X_EHCI_BASE 0x1b000000
81 #define AR913X_EHCI_SIZE 0x1000
82 #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
83 #define AR913X_WMAC_SIZE 0x30000
85 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
86 #define AR933X_UART_SIZE 0x14
87 #define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
88 #define AR933X_GMAC_SIZE 0x04
89 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
90 #define AR933X_WMAC_SIZE 0x20000
91 #define AR933X_EHCI_BASE 0x1b000000
92 #define AR933X_EHCI_SIZE 0x1000
94 #define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
95 #define AR934X_GMAC_SIZE 0x14
96 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
97 #define AR934X_WMAC_SIZE 0x20000
98 #define AR934X_EHCI_BASE 0x1b000000
99 #define AR934X_EHCI_SIZE 0x200
100 #define AR934X_NFC_BASE 0x1b000200
101 #define AR934X_NFC_SIZE 0xb8
102 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
103 #define AR934X_SRIF_SIZE 0x1000
105 #define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
106 #define QCA953X_GMAC_SIZE 0x14
107 #define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
108 #define QCA953X_WMAC_SIZE 0x20000
109 #define QCA953X_EHCI_BASE 0x1b000000
110 #define QCA953X_EHCI_SIZE 0x200
111 #define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
112 #define QCA953X_SRIF_SIZE 0x1000
114 #define QCA953X_PCI_CFG_BASE0 0x14000000
115 #define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
116 #define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
117 #define QCA953X_PCI_MEM_BASE0 0x10000000
118 #define QCA953X_PCI_MEM_SIZE 0x02000000
120 #define QCA955X_PCI_MEM_BASE0 0x10000000
121 #define QCA955X_PCI_MEM_BASE1 0x12000000
122 #define QCA955X_PCI_MEM_SIZE 0x02000000
123 #define QCA955X_PCI_CFG_BASE0 0x14000000
124 #define QCA955X_PCI_CFG_BASE1 0x16000000
125 #define QCA955X_PCI_CFG_SIZE 0x1000
126 #define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
127 #define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
128 #define QCA955X_PCI_CRP_SIZE 0x1000
129 #define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
130 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
131 #define QCA955X_PCI_CTRL_SIZE 0x100
133 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
134 #define QCA955X_GMAC_SIZE 0x40
135 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
136 #define QCA955X_WMAC_SIZE 0x20000
137 #define QCA955X_EHCI0_BASE 0x1b000000
138 #define QCA955X_EHCI1_BASE 0x1b400000
139 #define QCA955X_EHCI_SIZE 0x1000
140 #define QCA955X_NFC_BASE 0x1b800200
141 #define QCA955X_NFC_SIZE 0xb8
143 #define QCA956X_PCI_MEM_BASE1 0x12000000
144 #define QCA956X_PCI_MEM_SIZE 0x02000000
145 #define QCA956X_PCI_CFG_BASE1 0x16000000
146 #define QCA956X_PCI_CFG_SIZE 0x1000
147 #define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
148 #define QCA956X_PCI_CRP_SIZE 0x1000
149 #define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
150 #define QCA956X_PCI_CTRL_SIZE 0x100
152 #define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
153 #define QCA956X_WMAC_SIZE 0x20000
154 #define QCA956X_EHCI0_BASE 0x1b000000
155 #define QCA956X_EHCI1_BASE 0x1b400000
156 #define QCA956X_EHCI_SIZE 0x200
157 #define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
158 #define QCA956X_GMAC_SGMII_SIZE 0x64
159 #define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
160 #define QCA956X_PLL_SIZE 0x50
161 #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
162 #define QCA956X_GMAC_SIZE 0x64
167 #define QCA956X_MAC_CFG_BASE 0xb9000000
168 #define QCA956X_MAC_CFG_SIZE 0x64
170 #define QCA956X_MAC_CFG1_REG 0x00
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
178 #define QCA956X_MAC_CFG2_REG 0x04
184 #define QCA956X_MAC_CFG2_FDX BIT(0)
186 #define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
187 #define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
189 #define QCA956X_MAC_FIFO_CFG0_REG 0x48
190 #define QCA956X_MAC_FIFO_CFG1_REG 0x4c
191 #define QCA956X_MAC_FIFO_CFG2_REG 0x50
192 #define QCA956X_MAC_FIFO_CFG3_REG 0x54
193 #define QCA956X_MAC_FIFO_CFG4_REG 0x58
194 #define QCA956X_MAC_FIFO_CFG5_REG 0x5c
196 #define QCA956X_DAM_RESET_OFFSET 0xb90001bc
197 #define QCA956X_DAM_RESET_SIZE 0x4
203 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
204 #define AR71XX_DDR_REG_PCI_WIN1 0x80
205 #define AR71XX_DDR_REG_PCI_WIN2 0x84
206 #define AR71XX_DDR_REG_PCI_WIN3 0x88
207 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
208 #define AR71XX_DDR_REG_PCI_WIN5 0x90
209 #define AR71XX_DDR_REG_PCI_WIN6 0x94
210 #define AR71XX_DDR_REG_PCI_WIN7 0x98
211 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
212 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
213 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
214 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
216 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
217 #define AR724X_DDR_REG_FLUSH_GE1 0x80
218 #define AR724X_DDR_REG_FLUSH_USB 0x84
219 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
221 #define AR913X_DDR_REG_FLUSH_GE0 0x7c
222 #define AR913X_DDR_REG_FLUSH_GE1 0x80
223 #define AR913X_DDR_REG_FLUSH_USB 0x84
224 #define AR913X_DDR_REG_FLUSH_WMAC 0x88
226 #define AR933X_DDR_REG_FLUSH_GE0 0x7c
227 #define AR933X_DDR_REG_FLUSH_GE1 0x80
228 #define AR933X_DDR_REG_FLUSH_USB 0x84
229 #define AR933X_DDR_REG_FLUSH_WMAC 0x88
231 #define AR934X_DDR_REG_FLUSH_GE0 0x9c
232 #define AR934X_DDR_REG_FLUSH_GE1 0xa0
233 #define AR934X_DDR_REG_FLUSH_USB 0xa4
234 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
235 #define AR934X_DDR_REG_FLUSH_WMAC 0xac
237 #define QCA953X_DDR_REG_FLUSH_GE0 0x9c
238 #define QCA953X_DDR_REG_FLUSH_GE1 0xa0
239 #define QCA953X_DDR_REG_FLUSH_USB 0xa4
240 #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
241 #define QCA953X_DDR_REG_FLUSH_WMAC 0xac
246 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
247 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
248 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
249 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
252 #define AR71XX_PLL_FB_MASK 0x1f
254 #define AR71XX_CPU_DIV_MASK 0x3
256 #define AR71XX_DDR_DIV_MASK 0x3
258 #define AR71XX_AHB_DIV_MASK 0x7
263 #define AR724X_PLL_REG_CPU_CONFIG 0x00
264 #define AR724X_PLL_REG_PCIE_CONFIG 0x10
269 #define AR724X_PLL_FB_SHIFT 0
270 #define AR724X_PLL_FB_MASK 0x3ff
272 #define AR724X_PLL_REF_DIV_MASK 0xf
274 #define AR724X_AHB_DIV_MASK 0x1
276 #define AR724X_DDR_DIV_MASK 0x3
278 #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
280 #define AR913X_PLL_REG_CPU_CONFIG 0x00
281 #define AR913X_PLL_REG_ETH_CONFIG 0x04
282 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
283 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
285 #define AR913X_PLL_FB_SHIFT 0
286 #define AR913X_PLL_FB_MASK 0x3ff
288 #define AR913X_DDR_DIV_MASK 0x3
290 #define AR913X_AHB_DIV_MASK 0x1
295 #define AR933X_PLL_CPU_CONFIG_REG 0x00
296 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
299 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
301 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
303 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
307 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
309 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
311 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
313 #define AR934X_PLL_CPU_CONFIG_REG 0x00
314 #define AR934X_PLL_DDR_CONFIG_REG 0x04
315 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
316 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
317 #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
319 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
320 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
322 #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
324 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
326 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
328 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
329 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
331 #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
333 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
335 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
341 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
343 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
345 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
352 #define QCA953X_PLL_CPU_CONFIG_REG 0x00
353 #define QCA953X_PLL_DDR_CONFIG_REG 0x04
354 #define QCA953X_PLL_CLK_CTRL_REG 0x08
355 #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
356 #define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
357 #define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
359 #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
360 #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
362 #define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
364 #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
366 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
368 #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
369 #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
371 #define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
373 #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
375 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
381 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
383 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
385 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
390 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
391 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
392 #define QCA955X_PLL_CLK_CTRL_REG 0x08
393 #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
394 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
395 #define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
397 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
398 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
400 #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
402 #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
404 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
406 #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
407 #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
409 #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
411 #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
413 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
419 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
421 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
423 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
430 #define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
432 #define QCA956X_PLL_CPU_CONFIG_REG 0x00
433 #define QCA956X_PLL_CPU_CONFIG1_REG 0x04
434 #define QCA956X_PLL_DDR_CONFIG_REG 0x08
435 #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
436 #define QCA956X_PLL_CLK_CTRL_REG 0x10
437 #define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
438 #define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
439 #define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
442 #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
444 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
446 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
447 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
449 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
451 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
454 #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
456 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
458 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
459 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
461 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
463 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
469 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
471 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
473 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
482 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
495 #define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
501 #define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
506 #define AR71XX_USB_CTRL_REG_FLADJ 0x00
507 #define AR71XX_USB_CTRL_REG_CONFIG 0x04
512 #define AR71XX_RESET_REG_TIMER 0x00
513 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
514 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
515 #define AR71XX_RESET_REG_WDOG 0x0c
516 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
518 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
519 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
520 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
521 #define AR71XX_RESET_REG_RESET_MODULE 0x24
522 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
523 #define AR71XX_RESET_REG_PERFC0 0x30
524 #define AR71XX_RESET_REG_PERFC1 0x34
525 #define AR71XX_RESET_REG_REV_ID 0x90
527 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
528 #define AR913X_RESET_REG_RESET_MODULE 0x1c
529 #define AR913X_RESET_REG_PERF_CTRL 0x20
530 #define AR913X_RESET_REG_PERFC0 0x24
531 #define AR913X_RESET_REG_PERFC1 0x28
533 #define AR724X_RESET_REG_RESET_MODULE 0x1c
535 #define AR933X_RESET_REG_RESET_MODULE 0x1c
536 #define AR933X_RESET_REG_BOOTSTRAP 0xac
538 #define AR934X_RESET_REG_RESET_MODULE 0x1c
539 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
540 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
542 #define QCA953X_RESET_REG_RESET_MODULE 0x1c
543 #define QCA953X_RESET_REG_BOOTSTRAP 0xb0
544 #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
546 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
547 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
548 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
550 #define QCA956X_RESET_REG_RESET_MODULE 0x1c
551 #define QCA956X_RESET_REG_BOOTSTRAP 0xb0
552 #define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
566 #define MISC_INT_TIMER BIT(0)
585 #define AR71XX_RESET_PCI_CORE BIT(0)
644 #define AR934X_RESET_I2S BIT(0)
698 #define QCA955X_RESET_I2S BIT(0)
717 #define QCA956X_RESET_SWITCH BIT(0)
721 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
737 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
744 #define QCA953X_BOOTSTRAP_DDR1 BIT(0)
750 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
768 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
786 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
817 #define QCA956X_EXT_INT_WMAC_MISC BIT(0)
848 #define REV_ID_MAJOR_MASK 0xfff0
849 #define REV_ID_MAJOR_AR71XX 0x00a0
850 #define REV_ID_MAJOR_AR913X 0x00b0
851 #define REV_ID_MAJOR_AR7240 0x00c0
852 #define REV_ID_MAJOR_AR7241 0x0100
853 #define REV_ID_MAJOR_AR7242 0x1100
854 #define REV_ID_MAJOR_AR9330 0x0110
855 #define REV_ID_MAJOR_AR9331 0x1110
856 #define REV_ID_MAJOR_AR9341 0x0120
857 #define REV_ID_MAJOR_AR9342 0x1120
858 #define REV_ID_MAJOR_AR9344 0x2120
859 #define REV_ID_MAJOR_QCA9533 0x0140
860 #define REV_ID_MAJOR_QCA9533_V2 0x0160
861 #define REV_ID_MAJOR_QCA9556 0x0130
862 #define REV_ID_MAJOR_QCA9558 0x1130
863 #define REV_ID_MAJOR_TP9343 0x0150
864 #define REV_ID_MAJOR_QCA956X 0x1150
865 #define REV_ID_MAJOR_QCN550X 0x2170
867 #define AR71XX_REV_ID_MINOR_MASK 0x3
868 #define AR71XX_REV_ID_MINOR_AR7130 0x0
869 #define AR71XX_REV_ID_MINOR_AR7141 0x1
870 #define AR71XX_REV_ID_MINOR_AR7161 0x2
871 #define AR71XX_REV_ID_REVISION_MASK 0x3
874 #define AR913X_REV_ID_MINOR_MASK 0x3
875 #define AR913X_REV_ID_MINOR_AR9130 0x0
876 #define AR913X_REV_ID_MINOR_AR9132 0x1
877 #define AR913X_REV_ID_REVISION_MASK 0x3
880 #define AR933X_REV_ID_REVISION_MASK 0x3
882 #define AR724X_REV_ID_REVISION_MASK 0x3
884 #define AR934X_REV_ID_REVISION_MASK 0xf
886 #define QCA953X_REV_ID_REVISION_MASK 0xf
888 #define QCA955X_REV_ID_REVISION_MASK 0xf
890 #define QCA956X_REV_ID_REVISION_MASK 0xf
895 #define AR71XX_SPI_REG_FS 0x00 /* Function Select */
896 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
897 #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
898 #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
900 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
903 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f
905 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
908 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
917 #define AR71XX_GPIO_REG_OE 0x00
918 #define AR71XX_GPIO_REG_IN 0x04
919 #define AR71XX_GPIO_REG_OUT 0x08
920 #define AR71XX_GPIO_REG_SET 0x0c
921 #define AR71XX_GPIO_REG_CLEAR 0x10
922 #define AR71XX_GPIO_REG_INT_MODE 0x14
923 #define AR71XX_GPIO_REG_INT_TYPE 0x18
924 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
925 #define AR71XX_GPIO_REG_INT_PENDING 0x20
926 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
927 #define AR71XX_GPIO_REG_FUNC 0x28
929 #define AR934X_GPIO_REG_OUT_FUNC0 0x2c
930 #define AR934X_GPIO_REG_OUT_FUNC1 0x30
931 #define AR934X_GPIO_REG_OUT_FUNC2 0x34
932 #define AR934X_GPIO_REG_OUT_FUNC3 0x38
933 #define AR934X_GPIO_REG_OUT_FUNC4 0x3c
934 #define AR934X_GPIO_REG_OUT_FUNC5 0x40
935 #define AR934X_GPIO_REG_FUNC 0x6c
937 #define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
938 #define QCA953X_GPIO_REG_OUT_FUNC1 0x30
939 #define QCA953X_GPIO_REG_OUT_FUNC2 0x34
940 #define QCA953X_GPIO_REG_OUT_FUNC3 0x38
941 #define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
942 #define QCA953X_GPIO_REG_IN_ENABLE0 0x44
943 #define QCA953X_GPIO_REG_FUNC 0x6c
956 #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
957 #define QCA955X_GPIO_REG_OUT_FUNC1 0x30
958 #define QCA955X_GPIO_REG_OUT_FUNC2 0x34
959 #define QCA955X_GPIO_REG_OUT_FUNC3 0x38
960 #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
961 #define QCA955X_GPIO_REG_OUT_FUNC5 0x40
962 #define QCA955X_GPIO_REG_FUNC 0x6c
964 #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
965 #define QCA956X_GPIO_REG_OUT_FUNC1 0x30
966 #define QCA956X_GPIO_REG_OUT_FUNC2 0x34
967 #define QCA956X_GPIO_REG_OUT_FUNC3 0x38
968 #define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
969 #define QCA956X_GPIO_REG_OUT_FUNC5 0x40
970 #define QCA956X_GPIO_REG_IN_ENABLE0 0x44
971 #define QCA956X_GPIO_REG_IN_ENABLE3 0x50
972 #define QCA956X_GPIO_REG_FUNC 0x6c
990 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
991 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
992 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
994 #define AR934X_SRIF_DDR_DPLL1_REG 0x240
995 #define AR934X_SRIF_DDR_DPLL2_REG 0x244
996 #define AR934X_SRIF_DDR_DPLL3_REG 0x248
999 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
1001 #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
1002 #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1006 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
1008 #define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
1009 #define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
1010 #define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
1012 #define QCA953X_SRIF_DDR_DPLL1_REG 0x240
1013 #define QCA953X_SRIF_DDR_DPLL2_REG 0x244
1014 #define QCA953X_SRIF_DDR_DPLL3_REG 0x248
1017 #define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
1019 #define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
1020 #define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1024 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
1032 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
1050 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1081 #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1093 #define AR934X_GPIO_OUT_GPIO 0
1112 #define QCA955X_GPIO_OUT_GPIO 0
1171 #define AR71XX_MII_REG_MII0_CTRL 0x00
1172 #define AR71XX_MII_REG_MII1_CTRL 0x04
1177 #define AR71XX_MII_CTRL_SPEED_10 0
1181 #define AR71XX_MII0_CTRL_IF_GMII 0
1186 #define AR71XX_MII1_CTRL_IF_RGMII 0
1192 #define AR933X_GMAC_REG_ETH_CFG 0x00
1194 #define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
1203 #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
1209 #define AR934X_GMAC_REG_ETH_CFG 0x00
1211 #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
1225 #define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
1228 #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
1234 #define QCA953X_GMAC_REG_ETH_CFG 0x00
1245 #define QCA955X_GMAC_REG_ETH_CFG 0x00
1246 #define QCA955X_GMAC_REG_SGMII_SERDES 0x18
1248 #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
1258 #define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
1261 #define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
1263 #define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
1265 #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
1270 #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1275 #define QCA956X_GMAC_REG_ETH_CFG 0x00
1276 #define QCA956X_GMAC_REG_SGMII_RESET 0x14
1277 #define QCA956X_GMAC_REG_SGMII_SERDES 0x18
1278 #define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
1279 #define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
1280 #define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
1282 #define QCA956X_ETH_CFG_RGMII_EN BIT(0)
1289 #define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
1291 #define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
1294 #define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
1295 #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
1301 #define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
1303 #define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
1312 #define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1314 #define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
1319 #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
1320 #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7