Lines Matching +full:0 +full:xe0004000
15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
19 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
28 #define PICA_ASIC_REVISION 0xe0000008
43 * --------- . (0)
45 #define PICA_LED 0xe000f000
54 #define LED_DOT 0x01
55 #define LED_SPACE 0x00
56 #define LED_0 0xfc
57 #define LED_1 0x60
58 #define LED_2 0xda
59 #define LED_3 0xf2
60 #define LED_4 0x66
61 #define LED_5 0xb6
62 #define LED_6 0xbe
63 #define LED_7 0xe0
64 #define LED_8 0xfe
65 #define LED_9 0xf6
66 #define LED_A 0xee
67 #define LED_b 0x3e
68 #define LED_C 0x9c
69 #define LED_d 0x7a
70 #define LED_E 0x9e
71 #define LED_F 0x8e
87 #define JAZZ_ETHERNET_BASE 0xe0001000
92 #define JAZZ_SCSI_BASE 0xe0002000
99 #define JAZZ_KEYBOARD_ADDRESS 0xe0005000
100 #define JAZZ_KEYBOARD_DATA 0xe0005000
101 #define JAZZ_KEYBOARD_COMMAND 0xe0005001
129 #define MIPS_KEYBOARD_ADDRESS 0xb9005000
130 #define MIPS_KEYBOARD_DATA 0xb9005003
131 #define MIPS_KEYBOARD_COMMAND 0xb9005007
136 #define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000
137 #define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000
138 #define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000
143 #define JAZZ_DUMMY_DEVICE 0xe000d000
149 * it is remapped to vector 0. See arch/mips/kernel/entry.S.
151 #define JAZZ_TIMER_INTERVAL 0xe0000228
152 #define JAZZ_TIMER_REGISTER 0xe0000230
179 #define PICA_DRAM_CONFIG 0xe00fffe0
184 #define JAZZ_IO_IRQ_SOURCE 0xe0010000
185 #define JAZZ_IO_IRQ_ENABLE 0xe0010002
195 #define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0)
214 #define JAZZ_SCSI_DMA 0 /* SCSI */
223 #define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */
224 #define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */
225 #define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */
227 #define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */
228 #define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */
229 #define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */
231 #define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */
232 #define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */
233 #define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */
235 #define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */
236 #define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */
237 #define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */
238 #define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */
243 * 0: free, 1: Ethernet, 2: SCSI, 3: Floppy,
248 #define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */
249 /* 0xE0000070,78,80... 0xE00000E8 */
250 #define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */
251 #define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */
252 #define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */
253 #define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */
258 #define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */
304 #define JAZZ_FDC_BASE 0xe0003000
305 #define JAZZ_RTC_BASE 0xe0004000
306 #define JAZZ_PORT_BASE 0xe2000000
308 #define JAZZ_EISA_BASE 0xe3000000