Lines Matching +full:system +full:- +full:bus

10  * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
26 #define IOASIC_SYS_ROM	(0*IOASIC_SLOT_SIZE)	/* system board ROM */
36 #define IOASIC_ERRADDR	(9*IOASIC_SLOT_SIZE)	/* bus error address (3max+) */
38 #define IOASIC_ACC_BUS	(10*IOASIC_SLOT_SIZE)	/* ACCESS.bus (maxine) */
63 #define IO_REG_AB_T_DMA_P	0x50	/* ACCESS.bus Transmit DMA Pointer */
64 #define IO_REG_AB_R_DMA_P	0x60	/* ACCESS.bus Receive DMA Pointer */
72 #define IO_REG_DATA_0		0xc0	/* System Data Buffer 0 */
73 #define IO_REG_DATA_1		0xd0	/* System Data Buffer 1 */
74 #define IO_REG_DATA_2		0xe0	/* System Data Buffer 2 */
75 #define IO_REG_DATA_3		0xf0	/* System Data Buffer 3 */
78 #define IO_REG_SSR		0x100	/* System Support Register */
79 #define IO_REG_SIR		0x110	/* System Interrupt Register */
80 #define IO_REG_SIMR		0x120	/* System Interrupt Mask Reg. */
81 #define IO_REG_SAR		0x130	/* System Address Register */
96 #define IO_REG_AB_SLOT		0x190	/* ACCESS.bus DMA Slot Register */
100 #define IO_REG_SCSI_SCR		0x1b0	/* SCSI Partial-Word DMA Control */
103 #define IO_REG_FCTR		0x1e0	/* Free-Running Counter */
108  * The upper 16 bits of the System Support Register are a part of the
135 #define IO_SSR_AB_TX_DMA_EN	(1<<29)		/* ACCESS.bus xmit DMA enable */
136 #define IO_SSR_AB_RX_DMA_EN	(1<<28)		/* ACCESS.bus recv DMA enable */
143  * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
144  * defined here.  The rest is defined in system-specific headers.