Lines Matching +full:0 +full:x210000
58 #define CIU3_CONST 0x220
59 #define CIU3_IDT_CTL(_idt) ((_idt) * 8 + 0x110000)
60 #define CIU3_IDT_PP(_idt, _idx) ((_idt) * 32 + (_idx) * 8 + 0x120000)
61 #define CIU3_IDT_IO(_idt) ((_idt) * 8 + 0x130000)
62 #define CIU3_DEST_PP_INT(_pp_ip) ((_pp_ip) * 8 + 0x200000)
63 #define CIU3_DEST_IO_INT(_io) ((_io) * 8 + 0x210000)
64 #define CIU3_ISC_CTL(_intsn) ((_intsn) * 8 + 0x80000000)
65 #define CIU3_ISC_W1C(_intsn) ((_intsn) * 8 + 0x90000000)
66 #define CIU3_ISC_W1S(_intsn) ((_intsn) * 8 + 0xa0000000)
115 return 0; in octeon_irq_set_ciu_mapping()
137 if (ret < 0) in octeon_irq_force_ciu_mapping()
171 clear_c0_status(0x100 << bit); in octeon_irq_core_ack()
174 clear_c0_cause(0x100 << bit); in octeon_irq_core_ack()
186 set_c0_status(0x100 << cd->bit); in octeon_irq_core_eoi()
193 unsigned int mask = 0x100 << cd->bit; in octeon_irq_core_set_enable_local()
257 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) { in octeon_irq_init_core()
315 if (cd->line == 0) { in octeon_irq_ciu_enable()
347 if (cd->line == 0) { in octeon_irq_ciu_enable_local()
379 if (cd->line == 0) { in octeon_irq_ciu_disable_local()
414 if (cd->line == 0) in octeon_irq_ciu_disable_all()
426 if (cd->line == 0) in octeon_irq_ciu_disable_all()
447 if (cd->line == 0) in octeon_irq_ciu_enable_all()
459 if (cd->line == 0) in octeon_irq_ciu_enable_all()
484 if (cd->line == 0) { in octeon_irq_ciu_enable_v2()
568 if (cd->line == 0) { in octeon_irq_ciu_enable_local_v2()
587 if (cd->line == 0) { in octeon_irq_ciu_disable_local_v2()
609 if (cd->line == 0) { in octeon_irq_ciu_ack()
630 if (cd->line == 0) { in octeon_irq_ciu_disable_all_v2()
660 if (cd->line == 0) { in octeon_irq_ciu_enable_all_v2()
697 cfg.u64 = 0; in octeon_irq_gpio_setup()
699 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0; in octeon_irq_gpio_setup()
700 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; in octeon_irq_gpio_setup()
739 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio_v2()
749 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio()
812 return 0; in octeon_irq_ciu_set_affinity()
821 if (cd->line == 0) in octeon_irq_ciu_set_affinity()
838 if (cd->line == 0) in octeon_irq_ciu_set_affinity()
845 return 0; in octeon_irq_ciu_set_affinity()
862 return 0; in octeon_irq_ciu_set_affinity_v2()
867 if (cd->line == 0) { in octeon_irq_ciu_set_affinity_v2()
894 return 0; in octeon_irq_ciu_set_affinity_v2()
907 return 0; in octeon_irq_ciu_set_affinity_sum2()
922 return 0; in octeon_irq_ciu_set_affinity_sum2()
933 return 0; in edge_startup()
1080 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ in octeon_irq_ciu_wd_enable()
1130 if (line == 0) in octeon_irq_ciu_is_edge()
1173 pin = intspec[0]; in octeon_irq_gpio_xlat()
1202 return 0; in octeon_irq_gpio_xlat()
1215 ciu = intspec[0]; in octeon_irq_ciu_xlat()
1222 *out_type = 0; in octeon_irq_ciu_xlat()
1224 return 0; in octeon_irq_ciu_xlat()
1239 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0) in octeon_irq_ciu_map()
1244 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, in octeon_irq_ciu_map()
1248 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, in octeon_irq_ciu_map()
1253 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, in octeon_irq_ciu_map()
1257 rv = octeon_irq_set_ciu_mapping(virq, line, bit, 0, in octeon_irq_ciu_map()
1274 octeon_irq_ciu_to_irq[line][bit] != 0) in octeon_irq_gpio_map()
1307 int irq = octeon_irq_ciu_to_irq[0][bit]; in octeon_irq_ip2_ciu()
1390 __this_cpu_write(octeon_irq_ciu0_en_mirror, 0); in octeon_irq_init_ciu_percpu()
1391 __this_cpu_write(octeon_irq_ciu1_en_mirror, 0); in octeon_irq_init_ciu_percpu()
1399 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); in octeon_irq_init_ciu_percpu()
1400 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); in octeon_irq_init_ciu_percpu()
1401 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); in octeon_irq_init_ciu_percpu()
1402 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); in octeon_irq_init_ciu_percpu()
1417 * There are 9 registers and 3 IPX levels with strides 0x1000 in octeon_irq_init_ciu2_percpu()
1418 * and 0x200 respectively. Use loops to clear them. in octeon_irq_init_ciu2_percpu()
1420 for (regx = 0; regx <= 0x8000; regx += 0x1000) { in octeon_irq_init_ciu2_percpu()
1421 for (ipx = 0; ipx <= 0x400; ipx += 0x200) in octeon_irq_init_ciu2_percpu()
1422 cvmx_write_csr(base + regx + ipx, 0); in octeon_irq_init_ciu2_percpu()
1511 for (i = 0; i < 16; i++) { in octeon_irq_init_ciu()
1513 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0); in octeon_irq_init_ciu()
1519 if (r < 0) { in octeon_irq_init_ciu()
1524 OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq); in octeon_irq_init_ciu()
1528 if (r < 0) { in octeon_irq_init_ciu()
1533 OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq); in octeon_irq_init_ciu()
1537 for (i = 0; i < 4; i++) { in octeon_irq_init_ciu()
1539 ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36); in octeon_irq_init_ciu()
1543 for (i = 0; i < 4; i++) { in octeon_irq_init_ciu()
1545 ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40); in octeon_irq_init_ciu()
1550 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45); in octeon_irq_init_ciu()
1554 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46); in octeon_irq_init_ciu()
1558 for (i = 0; i < 4; i++) { in octeon_irq_init_ciu()
1560 ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52); in octeon_irq_init_ciu()
1565 r = octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59); in octeon_irq_init_ciu()
1570 if (r < 0) { in octeon_irq_init_ciu()
1575 for (i = 0; i < 16; i++) { in octeon_irq_init_ciu()
1577 i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd, in octeon_irq_init_ciu()
1590 return 0; in octeon_irq_init_ciu()
1610 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v); in octeon_irq_init_gpio()
1619 r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v0); in octeon_irq_init_gpio()
1653 return 0; in octeon_irq_init_gpio()
1670 (0x1000ull * cd->line); in octeon_irq_ciu2_wd_enable()
1687 (0x1000ull * cd->line); in octeon_irq_ciu2_enable()
1702 (0x1000ull * cd->line); in octeon_irq_ciu2_enable_local()
1718 (0x1000ull * cd->line); in octeon_irq_ciu2_disable_local()
1733 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd->line); in octeon_irq_ciu2_ack()
1749 octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd->line); in octeon_irq_ciu2_disable_all()
1814 return 0; in octeon_irq_ciu2_set_affinity()
1825 (0x1000ull * cd->line); in octeon_irq_ciu2_set_affinity()
1829 (0x1000ull * cd->line); in octeon_irq_ciu2_set_affinity()
1834 return 0; in octeon_irq_ciu2_set_affinity()
1850 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu2_disable_gpio()
1924 ciu = intspec[0]; in octeon_irq_ciu2_xlat()
1928 *out_type = 0; in octeon_irq_ciu2_xlat()
1930 return 0; in octeon_irq_ciu2_xlat()
1970 return 0; in octeon_irq_ciu2_map()
1972 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0) in octeon_irq_ciu2_map()
1976 octeon_irq_set_ciu_mapping(virq, line, bit, 0, in octeon_irq_ciu2_map()
1980 octeon_irq_set_ciu_mapping(virq, line, bit, 0, in octeon_irq_ciu2_map()
1984 return 0; in octeon_irq_ciu2_map()
2001 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful; in octeon_irq_ciu2()
2007 src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line); in octeon_irq_ciu2()
2082 for (i = 0; i < 64; i++) { in octeon_irq_init_ciu2()
2084 ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i); in octeon_irq_init_ciu2()
2089 for (i = 0; i < 32; i++) { in octeon_irq_init_ciu2()
2090 r = octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0, in octeon_irq_init_ciu2()
2096 for (i = 0; i < 4; i++) { in octeon_irq_init_ciu2()
2103 for (i = 0; i < 4; i++) { in octeon_irq_init_ciu2()
2110 for (i = 0; i < 4; i++) { in octeon_irq_init_ciu2()
2125 return 0; in octeon_irq_init_ciu2()
2192 unsigned int type = 0; in octeon_irq_cib_xlat()
2198 case 0: /* unofficial value, but we might as well let it work. */ in octeon_irq_cib_xlat()
2209 *out_hwirq = intspec[0]; in octeon_irq_cib_xlat()
2211 return 0; in octeon_irq_cib_xlat()
2236 return 0; in octeon_irq_cib_map()
2261 for (i = 0; i < host_data->max_bits; i++) { in octeon_irq_cib_handler()
2262 if ((bits & 1ull << i) == 0) in octeon_irq_cib_handler()
2300 parent_irq = irq_of_parse_and_map(ciu_node, 0); in octeon_irq_init_cib()
2312 r = of_address_to_resource(ciu_node, 0, &res); in octeon_irq_init_cib()
2314 pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node); in octeon_irq_init_cib()
2342 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ in octeon_irq_init_cib()
2343 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */ in octeon_irq_init_cib()
2353 return 0; in octeon_irq_init_cib()
2369 hwirq = intspec[0]; in octeon_irq_ciu3_xlat()
2377 case 0x04: /* Software handled separately. */ in octeon_irq_ciu3_xlat()
2391 case 0: /* unofficial value, but we might as well let it work. */ in octeon_irq_ciu3_xlat()
2401 return 0; in octeon_irq_ciu3_xlat()
2417 isc_w1c.u64 = 0; in octeon_irq_ciu3_enable()
2422 isc_ctl.u64 = 0; in octeon_irq_ciu3_enable()
2438 isc_w1c.u64 = 0; in octeon_irq_ciu3_disable()
2443 cvmx_write_csr(isc_ctl_addr, 0); in octeon_irq_ciu3_disable()
2463 isc_w1c.u64 = 0; in octeon_irq_ciu3_ack()
2479 isc_w1c.u64 = 0; in octeon_irq_ciu3_mask()
2496 isc_w1c.u64 = 0; in octeon_irq_ciu3_mask_ack()
2534 isc_w1c.u64 = 0; in octeon_irq_ciu3_set_affinity()
2539 isc_ctl.u64 = 0; in octeon_irq_ciu3_set_affinity()
2580 return 0; in octeon_irq_ciu3_mapx()
2624 if (ret < 0) { in octeon_irq_ciu3_ip2()
2628 isc_w1c.u64 = 0; in octeon_irq_ciu3_ip2()
2645 /* SW (mbox) are 0x04 in bits 12..19 */ in octeon_irq_ciu3_base_mbox_intsn()
2646 return 0x04000 + CIU3_MBOX_PER_CORE * core; in octeon_irq_ciu3_base_mbox_intsn()
2656 int local_core = octeon_coreid_for_cpu(cpu) & 0x3f; in octeon_irq_ciu3_mbox_intsn_for_cpu()
2677 if (likely(mbox >= 0 && mbox < CIU3_MBOX_PER_CORE)) { in octeon_irq_ciu3_mbox()
2683 isc_w1c.u64 = 0; in octeon_irq_ciu3_mbox()
2708 isc_w1s.u64 = 0; in octeon_ciu3_mbox_send()
2728 isc_ctl.u64 = 0; in octeon_irq_ciu3_mbox_set_enable()
2732 cvmx_write_csr(isc_ctl_addr, 0); in octeon_irq_ciu3_mbox_set_enable()
2736 isc_ctl.u64 = 0; in octeon_irq_ciu3_mbox_set_enable()
2776 isc_w1c.u64 = 0; in octeon_irq_ciu3_mbox_ack()
2817 cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip2), 0); in octeon_irq_ciu3_alloc_resources()
2818 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip2, 0), 1ull << core); in octeon_irq_ciu3_alloc_resources()
2819 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip2), 0); in octeon_irq_ciu3_alloc_resources()
2823 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip3, 0), 1ull << core); in octeon_irq_ciu3_alloc_resources()
2824 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip3), 0); in octeon_irq_ciu3_alloc_resources()
2828 cvmx_write_csr(b + CIU3_IDT_PP(idt_ip4, 0), 0); in octeon_irq_ciu3_alloc_resources()
2829 cvmx_write_csr(b + CIU3_IDT_IO(idt_ip4), 0); in octeon_irq_ciu3_alloc_resources()
2831 cvmx_write_csr(b + CIU3_IDT_CTL(unused_idt2), 0); in octeon_irq_ciu3_alloc_resources()
2832 cvmx_write_csr(b + CIU3_IDT_PP(unused_idt2, 0), 0); in octeon_irq_ciu3_alloc_resources()
2833 cvmx_write_csr(b + CIU3_IDT_IO(unused_idt2), 0); in octeon_irq_ciu3_alloc_resources()
2835 for (i = 0; i < CIU3_MBOX_PER_CORE; i++) { in octeon_irq_ciu3_alloc_resources()
2839 cvmx_write_csr(b + CIU3_ISC_CTL(intsn), 0); in octeon_irq_ciu3_alloc_resources()
2842 return 0; in octeon_irq_ciu3_alloc_resources()
2883 node = 0; /* of_node_to_nid(ciu_node); */ in octeon_irq_init_ciu3()
2889 ret = of_address_to_resource(ciu_node, 0, &res); in octeon_irq_init_ciu3()
2910 WARN_ON(i < 0); in octeon_irq_init_ciu3()
2912 for (i = 0; i < 8; i++) in octeon_irq_init_ciu3()
2923 for (i = 0; i < MAX_CIU3_DOMAINS; i++) in octeon_irq_init_ciu3()
2931 if (node == 0) in octeon_irq_init_ciu3()
2940 return 0; in octeon_irq_init_ciu3()